expression cannot be folded

[michg]

Thanks a lot for fixing the last issue. Now a very ugly one:
library ieee;
use ieee.std_logic_1164.all;

entity comp6_bot is
generic (num : integer := 2 );
port (
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0) );
end entity;

architecture rtl of comp6_bot is

function cfunc (constant val : integer) return integer is
variable tmp : integer;
begin tmp := 0;
for i in 0 to 3 loop
tmp := tmp + val;
end loop;
return tmp;
end function cfunc;

constant cnum : integer := cfunc(num);
type m_a_t is array (cnum-1 downto 0) of std_logic_vector(num-1 downto 0);
signal ma : m_a_t;

begin
y <= x;
end architecture;

---

library ieee;
use ieee.std_logic_1164.all;

entity comp6 is
end entity;

architecture rtl of comp6 is
signal b: std_logic_vector(7 downto 0);

component comp6_bot is
    generic (num : integer := 2 ); 
    port (
        y : out std_logic_vector(7 downto 0);
        x : in std_logic_vector(7 downto 0) );
end component;

begin

c1: component comp6_bot
generic map (num => 8)  
    port map ( x=>x"aa", y=>b );

end architecture;

[nickg]

Not as easy to fix as the others unfortunately. Can you try with the latest version?

[michg]

Thanks. Seems, that my test case is not good enough. With the original code I am still getting the same error.

[michg]

Here a slightly different test case:
library ieee;
use ieee.std_logic_1164.all;

entity comp7_bot is
generic (num : integer := 2 );
port (
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0) );
end entity;

architecture rtl of comp7_bot is

function cfunc (constant k : integer) return integer is
variable tmp : integer;
begin
tmp := 1;
for i in 0 to k loop
if tmp > k then
return i;
end if;
tmp := tmp + tmp;
end loop;
end cfunc;

constant cnum : integer := cfunc(num);
type m_a_t is array (cnum-1 downto 0) of std_logic_vector(num-1 downto 0);
signal ma : m_a_t;

begin
y <= x;
end architecture;

---

library ieee;
use ieee.std_logic_1164.all;

entity comp7 is
end entity;

architecture rtl of comp7 is
signal b: std_logic_vector(7 downto 0);

component comp7_bot is
    generic (num : integer := 2 ); 
    port (
        y : out std_logic_vector(7 downto 0);
        x : in std_logic_vector(7 downto 0) );
end component;

begin

c1: component comp7_bot
generic map (num => 8)  
    port map ( x=>x"aa", y=>b );

end architecture;

[nickg]

How about now?

[michg]

Better, but still not entirely working. Sorry:

library ieee;
use ieee.std_logic_1164.all;

entity comp8_bot is
generic (num : integer := 2 );
port (
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0) );
end entity;

architecture rtl of comp8_bot is

function cfunc (constant k : integer) return integer is
variable tmp : integer;
begin
tmp := 1;
for i in 0 to k loop
if tmp > k then
return i;
end if;
tmp := tmp + tmp;
end loop;
end cfunc;

function my_cfunc (constant k: integer) return integer is
begin
if k > 1 then
return cfunc(k);
end if;
return 1;
end my_cfunc;

constant cnum : integer := my_cfunc(num);
type m_a_t is array (cnum-1 downto 0) of std_logic_vector(num-1 downto 0);
signal ma : m_a_t;

begin
y <= x;
end architecture;

---

library ieee;
use ieee.std_logic_1164.all;

entity comp8 is
end entity;

architecture rtl of comp8 is
signal b: std_logic_vector(7 downto 0);

 component comp8_bot is
    generic (num : integer := 2 ); 
    port (
        y : out std_logic_vector(7 downto 0);
        x : in std_logic_vector(7 downto 0) );
end component;

begin

c1: component comp8_bot
generic map (num => 8)  
    port map ( x=>x"aa", y=>b );

end architecture;

[nickg]

Improved this some more in the above commit

[michg]

Thanks, good work. #19 is fine with the latest commit. I am getting now: array signals with more than one dimension are not supported yet. I am optimistic, that you are going to implement this feature in the near future?

[nickg]

Yup it's on the TODO list

[nickg]

I've added some support for multidimensional arrays now. Not sure if it'll work well enough for your code but I added a simple test case in commit 1524c98 which runs now.

[michg]

Thanks. Now with the new commit I am getting assertion "false" failed file "../../src/group.c", line 291. Maybe you could expand the error message there to determine the causing source code?

[nickg]

Added location information in commit aa9ba32. I suspect it's something like foo(a)(x to y) which should be simple to support. Can you open a separate bug report for this? Thanks.

[michg]

My latest error was due a bad written testbench, so therefor no further action is necessary. Now I reach the
maximum file limit assertion "findex!=MAX_FILES" failed. Is it possible to increase it ?. I have roughly 250 source files. Thanks a lot.

[nickg]

Increased it to 512. Commit 3e8152

[michg]

Thanks, now new assertion "!cgen_const_bounds(arg_types[1]" failed file cgen.c line 2277 function: cgen_fcall.
Maybe more debug information there would help?

[nickg]

I'm not actually sure why that assertion is there. I've removed it in commit 92bd8af

[michg]

No success, now I am getting an endless loop of "Broken module found, verification continues.", mixed with
"Invalid InsertValueInst operands! %23=insertvalue(i8, [1x{i32,i32,i8}]} undef, i32* %18,0"". Any ideas?

[nickg]

Bit of a guess but can you see if commit c882480 helps?

[michg]

With the latest commit a small change: now mixed message is %MASTER498 = alloca i32
%MASTER = insertvalue {i32_,i32_} undef, i32* %MASTER,0 .

[nickg]

Can you include a bit more of the output? There should be an error message before or after that line

[michg]

With the latest commits I am getting new errors in the analysis stage: type of aggregate is ambigous
IEEE.STD_LOGIC_ARITH.UNSIGNED
IEEE.STD_LOGIC_ARITH.SIGNED
But STD_LOGIC_ARITH is not used in the reported file.

[nickg]

Should be fixed now

[michg]

Is fixed, so now previous error: The first error message is
Call parameter type does not match function signature!
%MASTER86= inserttvalue {{ i32_,o32_},{i8_,[1 x {i32,i32,i8}], {i8_...

[nickg]

Can you include a bit more of the error message? It also might be helpful to include the relevant bit of generated LLVM IR which you can get with:

nvc -e <top> --dump-llvm 2>&1 | grep -C 5 MASTER86

[michg]

I have attached a screenshot of the first messages. I am not able to interpret it.

[nickg]

Have you got a function that looks something like this?

function owns_master_slave(a, b, c, d : std_logic) return boolean;

Maybe try narrowing it down to the places that call that.

[michg]

Good hint. This last error was caused by functions with the same name in different processes, something like this:
architecture rtl of xy is
begin
p1: process
function owns_master_slave return boolean;
begin
end process
p2: process
function owns_master_slave return boolean;
begin
end process
end xy
If I use only one global function, the error message changes to:
Instruction does not dominate all uses!
%MASTER=alloca i32
%MASTER=insertvalue{i32_,i32_} undef, i32* %MASTER,0
Broken module found, verification continues.
Any ideas?

[nickg]

Is there a variable called "master" in a process or function somewhere?

[nickg]

The function name collision should be fixed now BTW