using enumaration type in loop_parameter_specification

[hiyuh]

VHDL-1993 allows to use enumaration type in loop_parameter_specification.

loop_statement ::= 
 [ loop_label : ]
 [ iteration_scheme ] loop
  sequence_of_statements
  end loop [ loop_label ] ;

iteration_scheme ::=
 while condition
 | for loop_parameter_specification

parameter_specification ::=
 identifier in discrete_range

discrete_range ::= discrete_subtype_indication | range

subtype_indication ::=
 [ resolution_function_name ] type_mark [ constraint ]

type_mark ::=
 type_name
 | subtype_name

w/ proposed issueZ,

entity issueZ is
begin
end entity issueZ;

architecture a of issueZ is
    type t is (e0, e1, e2, e3);
begin
    p : process
    begin
        f : for v in t loop
            report t'image(v);
        end loop f;
        wait;
    end process p;
end architecture a;

then i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc.exe -a test/regress/issueZ.vhd
** Error: invalid range expression
        File test/regress/issueZ.vhd, Line 10
      f : for v in t loop
                   ^

[nickg]

Should be fixed by the above commit