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I found this example in a project that is hard to share in order for you to reproduce. But I was able to reproduce it using a dummy statement in a simpler TB.
This seems to be a VHDL parser problem. It expects either a constant, signal or variable. But then it complains that a constant was unexpected.
To reproduce open a console, go to folder fw, and execute:
python3 -u ./sim/run.py -o ./sim/vunit_out/nvc --simulator nvc --simulator-path C:/NVC_1_13_2/bin --vendor-lib ./fw/sim/sim_lib/nvc --compile
Please adapt the path of the NVC installation folder in the command above (see --simulator-path).
The text was updated successfully, but these errors were encountered:
I found this example in a project that is hard to share in order for you to reproduce. But I was able to reproduce it using a dummy statement in a simpler TB.
This seems to be a VHDL parser problem. It expects either a
constant
,signal
orvariable
. But then it complains that aconstant
was unexpected.This compile fines in GHDL, Questa or Modelsim.
nvc_bug_3.zip
To reproduce open a console, go to folder fw, and execute:
python3 -u ./sim/run.py -o ./sim/vunit_out/nvc --simulator nvc --simulator-path C:/NVC_1_13_2/bin --vendor-lib ./fw/sim/sim_lib/nvc --compile
Please adapt the path of the NVC installation folder in the command above (see --simulator-path).
The text was updated successfully, but these errors were encountered: