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1. BIST-Design BIST-Design Public

   Done as a part of the coursework, Design For Testing and Testability. Designed and implemented in Verilog to add Built in Self Test (BIST) capabilities to a given combinational logic. The Test Patt…

   Verilog 2 1

2. 16bit-ALU-design 16bit-ALU-design Public

   Design of a 16-bit ALU using Verilog HDL. Done as a part of the coursework advanced digital system design using Verilog HDL.

   Verilog

3. wafer-fault-detection wafer-fault-detection Public

   Built a classification methodology to predict the quality of wafer sensors based on the given training data.

   Python

4. SD-WAN SD-WAN Public

   SD-WAN DEMO