Prefetch Everywhere

[larsbrinkhoff]

This makes all instructions do one prefetch cycle. So far I have not considered the placement of the prefetch inside the old instructions. The clocked instructions does it right, except some should also have an additional prefetch.

The treatment of instructions using ea_set_prefetch_before_write is not very good. Presumably, EA calculation should fetch words from the prefetch queue, and refill it.

[larsbrinkhoff]

There was one strange thing I stumbled across: prefetch in the old MOVEM. The code calls cpu_prefetch once for each register written. I don't know why, but it doesn't seem right.

The clocked MOVEM gained a new state at the end to do a prefetch. This is in line with the Yacht table.

[stefanberndtsson]

I think that old MOVEM stuff was just a mistake. Things went a bit quick to stuff cpu_prefetch-lines in there.

[stefanberndtsson]

I think we need to find a way to introduce the irc/ir/ird steps of the prefetch (and stop loading yacht-"p":s manually). To make the clocked instructions and a proper generic EA there, the current naive prefetch doesn't really cut it, and trying to make both of them work at once doesn't really seem sensible.

[larsbrinkhoff]

Yes, my next step was to do the full IRC/IR/IRD thing.

This work only applies to the old CPU.

[stefanberndtsson]

Ahh... Good.. It'll help a lot in clocked stuff :)

[larsbrinkhoff]

I keep forgetting to state why I'm making a change.

The overall purpose of this work is to:

1. Remove the need for a hard-coded wait state in cpu.c.
2. Make some instructions pair, so that Level 16 "Full Screen", and TOS-Crew "Rasters" work.

All instructions with a prefetch cycle last will effectively be synchronised with the MMU. That should take care of the first point.

Special attention to the bus accesses in MOVE, ADD, CMP, and Bcc will then ensure those instructions pair as expected.

[larsbrinkhoff]

@stefanberndtsson I added proper prefetch to all clocked instructions.

Due to the use of ASSERT in fetch_instr and cpu_prefetch, we can be sure that the prefetch queue stays balanced at all times.

[larsbrinkhoff]

Even though there is still more prefetch work to do, I consider this useful and complete enough to submit for merging.

All instructions now do some prefetching. When running from RAM, this synchronises the CPU with the MMU bus cycles. So wait states can be done properly.

Also, the new clocked instructions can now work with the prefetch queue, and do prefetch bus cycles in the right places.

[larsbrinkhoff]

Level 16 Full Screen Demo now works fully, including the first part with PSG accesses.

BIG Demo still loads.

Phalanx Demo F1 took a hit. Sometimes the lower border switch to low resolution comes too late. Probably related to exception timing.