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A pipelined implementation of a MIPS Processor.
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Latest commit 8be4912 Nov 16, 2013
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asm
.gitignore added slides' Nov 16, 2013
LAB2.vhd
Lab3_Group42_CG3207.pptx
adder32.vhd
addsub32.vhd
alu.vhd
control_unit.vhd r type instruction decoding Oct 23, 2013
cpu.vhd Final commit :3 Nov 14, 2013
decode.vhd
div32.vhd Changed from int to std_logic_vector \div32 Nov 13, 2013
fetch.vhd
funct_to_alu.vhd r type instruction decoding Oct 23, 2013
mul32.vhd
pipe_arith.bit
pipe_calc.bit BGEZAL working with pipeline Nov 13, 2013
pipe_comp.bit BGEZAL working with pipeline Nov 13, 2013
pipe_comp_bgezal.bit
pipe_div.bit
pipe_div_sll.bit
pipe_div_sll_slv.bit
pipe_sr.bit
ram.vhd
ram_test.vhd FAST RAM BITCHES Oct 30, 2013
rom.vhd Final commit :3 Nov 14, 2013
rom_test.vhd
test_adder32.vhd
test_addsub32.vhd
test_alu.vhd DIE RIZWAN BHAI Oct 30, 2013
test_control_unit.vhd shifting rom and rams to comninational. Weird shit fucks Oct 18, 2013
test_cpu.vhd Final commit :3 Nov 14, 2013
test_decode.vhd intergration WIP. Sooo sleeeeeppy Oct 23, 2013
test_div32.vhd Added mul,umul,div,udiv Oct 9, 2013
test_fetch.vhd Before shifting rom to comninational... again Oct 23, 2013
test_mul32.vhd
test_uadder32.vhd uadder32 tested Oct 2, 2013
test_uaddsub32.vhd
test_udiv32.vhd Removed redundant comparators from div32 Nov 13, 2013
test_umul32.vhd Added mul,umul,div,udiv Oct 9, 2013
uadder32.vhd uadder32 tested Oct 2, 2013
uaddsub32.vhd unsiged addsub tested and working Oct 5, 2013
udiv32.vhd Working... for now Oct 10, 2013
umul32.vhd
utils.vhd FINALLY MAPPED WITH 94%. Added logic for address decoding when readin… Nov 13, 2013
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