Example code for "8 RISC-V cores and a USB core"?

[nalzok]

Hi Olof, a few days ago you announced an interesting result on Twitter:

Can you probably share the code with us? I have a TinyFPGA-BX and would love to try it out. While working on a similar project, I had some problems (e.g. this issue) using tinyfpga_bx_usbserial. Your demo would serve as a great example for me and other beginners.

[olofk]

Hi. The project is available here https://github.com/olofk/corescore

[nalzok]

Awesome! Just a few notes for others wondering the same.

1. You need to manually install the usbserial dependency for the TinyFPGA target, otherwise, there will be a "dependency not available" error

fusesoc library add usbserial https://github.com/davidthings/tinyfpga_bx_usbserial 

2. You need to manually apply this pull request to the tinyfpga_bx_usbserial repository, otherwise, Nextpnr will not be able to meet the timing constraint.

3. To run corescore/sw/corecount.py, you need to install

pip install u-msgpack-python

Feel free to close this issue if you don't have further comments :)

[davidthings]

The PR nalzok mentions above is now accepted, obviating the need for step 2 above.

[olofk]

Great. Thanks for informing. Still need to write down the other parts. :)

[olofk]

I think this would be more suitable to submit as a bug to CoreScore instead of SERV, so I'm closing now