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ombhilare999/README.md

Omkar Bhilare

(Digital Design and Verification Enthusiast)

I'm a final year electronics undergraduate student and I do have great interest in Digital VLSI, FPGA prototyping, RTL Design and verification. In my undergrad I have tinkered a lot with FPGAs, Microcontrollers and circuit designs. I have made my small RISC-V core in verilog. Also made a 8 bit computer using SAP (Simple as possible!) Logic and simulated it in Logisim.
I'm a former verification Research Intern at SHAKTI , RISE LAB, IITM. SHAKTI is an open-source initiative by RISE group at IIT-Madras with the aim to produce production grade processors, complete System on Chips (SoCs), development boards and SHAKTI-based software platform. I was selected in Google Summer of Code 2021 (GSOC'21) with beagleboard org. I had worked on a FPGA cape named BeagleWire and developed Gateware for it.
I'm always open to Research opportunities in Computer Architecture, RTL Design, Verification and FPGA prototyping.

Pinned

  1. BeagleWire BeagleWire Public

    Forked from BeagleWire/BeagleWire

    This repository contains software for BeagleWire. Docs of BeagleWire: https://beaglewire.github.io/

    Verilog 1

  2. SRA-VJTI/sra-board-hardware-design SRA-VJTI/sra-board-hardware-design Public

    ESP32-based Development Board for Robotics and Embedded Applications

    66 23

  3. riscv-core riscv-core Public

    A customized RISCV core made using verilog

    Verilog 15 3

  4. 8-bit-computer 8-bit-computer Public

    8 bit computer using sap logic

    Python 6

  5. vga-interface-with-TANG-PRIMER-FPGA vga-interface-with-TANG-PRIMER-FPGA Public

    Interfacing Tang primer with VGA display.

    Verilog 8

  6. 8-Bit-ALU-implementation-on-CYCLONE-2 8-Bit-ALU-implementation-on-CYCLONE-2 Public

    Verilog code for 8 Bit ALU and implemented on Intel's Cyclone II

    Verilog