Add RISC-V clang build #2737
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Add RISC-V clang build #2737
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keeranroth
requested review from
Alexsandruss,
samir-nasibli,
Alexandr-Solovev,
napetrov,
homksei,
ahuber21 and
ethanglaser
as code owners
|
Based on top of #2736 |
luhenry
reviewed
Apr 22, 2024
luhenry
approved these changes
Apr 22, 2024
|
/intelci: run |
1 similar comment
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/intelci: run |
We add a RISC-V target. We are interested in higher-performance cores, so make sure that the vector extension is in place for this. The functionality is on par with aarch64 cross builds. CI is added as well. We assume that the RISC-V target has vector extensions enabled, and that this is at least 128-bits long. This is in line with RISC-V International guidelines that application class processors have a vector length >= 128-bits There are some modifications of the toolchain that are required to get vector support up and running. In particular, a newer qemu is required, and this needs to be set up with binfmt support, as the deb package does not automatically setup binfmt. Changes made: * Add ability to install LLVM from an upstream repo * Pass the architecture to install GNU cross-compilers to apt.sh * Add ability to install qemu from a Debian package * Add a file for setting up binfmt to run RISC-V binaries without specifying QEMU on the command line * Add clang CMake toolchain file for RISC-V * Add a CI pipeline for running and testing (under emulation) RISC-V builds using LLVM * Allow the architecture string in the PLATFORM variable to be more than 3 characters long, so that we can use riscv64 as the architecture name in the oneDAL build * Update openBLAS builds to use RISC-V optimized builds with 128-bit vector length * Add a precompile macro TARGET_RISCV64 to identify when the build is targeting RISC-V, in order to target RISC-V specific parts of the code base * Add structs, macros and enums, as per the SVE build, so that future commits can target specific micro-architectures more easily, and so that the current build completes for RISC-V * Add a cpu_vendor to all builds for riscv64 * Add lnxriscv64 as a platform to use in the makefile
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/intelci: run |
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@Alexandr-Solovev are there some things that need fixing? The public CI is green, and there aren't any outstanding comments |
napetrov
approved these changes
Apr 25, 2024
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Private CI - looks as sporadic GPU hang that shouldn't be related. @Alexandr-Solovev - please confirm
Alexandr-Solovev
approved these changes
Apr 26, 2024
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Description
We add a RISC-V target. We are interested in higher-performance cores, so make sure that the vector extension is in place for this. The functionality is on par with aarch64 cross builds. CI is added as well. We assume that the RISC-V target has vector extensions enabled, and that this is at least 128-bits long. This is in line with RISC-V International guidelines that application class processors have a vector length >= 128-bits
There are some modifications of the toolchain that are required to get vector support up and running. In particular, a newer qemu is required, and this needs to be set up with binfmt support, as the deb package does not automatically setup binfmt.
Changes proposed: