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Self Save: Fixing self save of core SPR.
Commit fixes - the issue originated due to withdrawal of self-save for HRMOR and URMOR. This withdrawal created an asymmetry in the design of self-save and restore. Commit fixes the self-save common routine which now accounts for not self saving of HRMOR. - missing handling of an LE core in STOP entry path. Key_Cronus_Test=PM_REGRESS Change-Id: I3bcdb9b0a4c6e0c99b2731c5253872f2ffb41244 Original-Change-Id: I9a10b4ff0062980ed496d93976a2a30a6f31af77 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75808 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
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2 files changed

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‎import/chips/p9/procedures/utils/stopreg/p9_core_save_restore_routines.S

Lines changed: 44 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -127,7 +127,7 @@
127127
.set USRR0, 506
128128
.set USRR1, 507
129129
.set SMFCTRL, 511 # Ultravisor
130-
.set HID0, 1008
130+
.set HID, 1008
131131
.set PIR, 1023
132132

133133
#--------------------SPR definition ends---------------------------------------
@@ -168,6 +168,17 @@
168168
.set SELF_REST_VER_INFO_OFFSET, 0x1C
169169
.set SMF_SIGNATURE_OFFSET, 0x1300
170170
.set SMF_SIGNATURE_CONST, 0x5f534d46 # '_SMF'
171+
.set HILE_BIT_POS, 4
172+
.set LE_BIT_POS, 63
173+
.set MF_HRMOR_R1, 0xa64a397c
174+
.set CLEAR_MSR_LE, 0xa407b57a
175+
.set MT_SRR1, 0xa603bb7e
176+
.set ADDI_R1_32, 0x20012138
177+
.set MT_SRR0_R1, 0xa6033a7c
178+
.set RFID, 0x2400004c
179+
.set TRAP_LE, 0x0800e07f
180+
.set MFMSR_R21, 0xa600a07e
181+
171182

172183
.set SPR_SAVE_SCRATCH_REG, r0
173184
.set SPR_DATA_REG, r1
@@ -285,6 +296,34 @@ _start:
285296

286297
_sreset_hndlr:
287298

299+
b big_endian_start
300+
301+
little_endian_start:
302+
.long MF_HRMOR_R1
303+
.long MFMSR_R21
304+
.long CLEAR_MSR_LE
305+
.long MT_SRR1
306+
.long ADDI_R1_32
307+
.long MT_SRR0_R1
308+
.long RFID
309+
310+
#Note: below are instructions for swizzled machine code used above for
311+
#LE core entering STOP
312+
#mfspr r1, HRMOR
313+
#mfmsr MSR_INIT_REG
314+
#clrrdi MSR_INIT_REG, MSR_INIT_REG, 1
315+
#mtsrr1 MSR_INIT_REG
316+
#addi r1, r1, 288
317+
#mtsrr0 r1
318+
#rfid
319+
320+
321+
322+
big_endian_start:
323+
mfspr SPR_DATA_REG, HID
324+
li TEMP_REG1, 0
325+
insrdi SPR_DATA_REG, TEMP_REG1, 1, HILE_BIT_POS
326+
mtspr HID, SPR_DATA_REG # Cleared HILE bit position
288327
mfmsr MSR_INIT_REG
289328
ori MSR_INIT_REG, MSR_INIT_REG, MACHINE_CHECK_ENABLE_CONST # Set the ME bit
290329
extrdi. MSR_SECURITY_ENABLE_REG, MSR_INIT_REG, 1, MSR_SECURITY_BIT # read Secure Bit (S) of MSR
@@ -782,7 +821,10 @@ cmpwi THREAD_ID_REG, 0 # if thread in question is 0, also,
782821
bne save_restore_done # else saving of SPRs is done
783822

784823
save_core_spr:
785-
addi SELF_RESTORE_ADDR_REG, CORE_SCOPE_RESTORE_ADDR_REG, 8
824+
# 8B for mflr r30
825+
# 32B for skipping HRMOR restore entry
826+
# Self save should start at an offset 8B + 32B = 40B
827+
addi SELF_RESTORE_ADDR_REG, CORE_SCOPE_RESTORE_ADDR_REG, 40
786828
mtlr CORE_SELF_SAVE_BASE_ADDR
787829
blrl
788830

‎import/chips/p9/procedures/utils/stopreg/p9_core_save_restore_routines.s

Lines changed: 44 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,7 @@
131131
.set USRR0, 506
132132
.set USRR1, 507
133133
.set SMFCTRL, 511 # Ultravisor
134-
.set HID0, 1008
134+
.set HID, 1008
135135
.set PIR, 1023
136136

137137
#--------------------SPR definition ends---------------------------------------
@@ -172,6 +172,17 @@
172172
.set SELF_REST_VER_INFO_OFFSET, 0x1C
173173
.set SMF_SIGNATURE_OFFSET, 0x1300
174174
.set SMF_SIGNATURE_CONST, 0x5f534d46 # '_SMF'
175+
.set HILE_BIT_POS, 4
176+
.set LE_BIT_POS, 63
177+
.set MF_HRMOR_R1, 0xa64a397c
178+
.set CLEAR_MSR_LE, 0xa407b57a
179+
.set MT_SRR1, 0xa603bb7e
180+
.set ADDI_R1_32, 0x20012138
181+
.set MT_SRR0_R1, 0xa6033a7c
182+
.set RFID, 0x2400004c
183+
.set TRAP_LE, 0x0800e07f
184+
.set MFMSR_R21, 0xa600a07e
185+
175186

176187
.set SPR_SAVE_SCRATCH_REG, r0
177188
.set SPR_DATA_REG, r1
@@ -289,6 +300,34 @@ _start:
289300

290301
_sreset_hndlr:
291302

303+
b big_endian_start
304+
305+
little_endian_start:
306+
.long MF_HRMOR_R1
307+
.long MFMSR_R21
308+
.long CLEAR_MSR_LE
309+
.long MT_SRR1
310+
.long ADDI_R1_32
311+
.long MT_SRR0_R1
312+
.long RFID
313+
314+
#Note: below are instructions for swizzled machine code used above for
315+
#LE core entering STOP
316+
#mfspr r1, HRMOR
317+
#mfmsr MSR_INIT_REG
318+
#clrrdi MSR_INIT_REG, MSR_INIT_REG, 1
319+
#mtsrr1 MSR_INIT_REG
320+
#addi r1, r1, 288
321+
#mtsrr0 r1
322+
#rfid
323+
324+
325+
326+
big_endian_start:
327+
mfspr SPR_DATA_REG, HID
328+
li TEMP_REG1, 0
329+
insrdi SPR_DATA_REG, TEMP_REG1, 1, HILE_BIT_POS
330+
mtspr HID, SPR_DATA_REG # Cleared HILE bit position
292331
mfmsr MSR_INIT_REG
293332
ori MSR_INIT_REG, MSR_INIT_REG, MACHINE_CHECK_ENABLE_CONST # Set the ME bit
294333
extrdi. MSR_SECURITY_ENABLE_REG, MSR_INIT_REG, 1, MSR_SECURITY_BIT # read Secure Bit (S) of MSR
@@ -786,7 +825,10 @@ cmpwi THREAD_ID_REG, 0 # if thread in question is 0, also, save core SPRs
786825
bne save_restore_done # else saving of SPRs is done
787826

788827
save_core_spr:
789-
addi SELF_RESTORE_ADDR_REG, CORE_SCOPE_RESTORE_ADDR_REG, 8
828+
# 8B for mflr r30
829+
# 32B for skipping HRMOR restore entry
830+
# Self save should start at an offset 8B + 32B = 40B
831+
addi SELF_RESTORE_ADDR_REG, CORE_SCOPE_RESTORE_ADDR_REG, 40
790832
mtlr CORE_SELF_SAVE_BASE_ADDR
791833
blrl
792834

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