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Self Save: Fixing self save of core SPR.
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Commit fixes
    -   the issue originated due to withdrawal of self-save
        for HRMOR and URMOR. This withdrawal created an
        asymmetry in the design of self-save and restore.
        Commit fixes the self-save common routine which
        now accounts for not self saving  of HRMOR.
    -   missing handling of an LE core in STOP entry path.
Key_Cronus_Test=PM_REGRESS

Change-Id: I3bcdb9b0a4c6e0c99b2731c5253872f2ffb41244
Original-Change-Id: I9a10b4ff0062980ed496d93976a2a30a6f31af77
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75808
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
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@premsjha @op-jenkins
premsjha authored and op-jenkins committed Jan 18, 2020
1 parent 694afd6 commit 065c07c
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Showing 2 changed files with 88 additions and 4 deletions.
46 changes: 44 additions & 2 deletions import/chips/p9/procedures/utils/stopreg/p9_core_save_restore_routines.S
View file
Expand Up @@ -127,7 +127,7 @@
.set USRR0, 506
.set USRR1, 507
.set SMFCTRL, 511 # Ultravisor
.set HID0, 1008
.set HID, 1008
.set PIR, 1023

#--------------------SPR definition ends---------------------------------------
Expand Down Expand Up @@ -168,6 +168,17 @@
.set SELF_REST_VER_INFO_OFFSET, 0x1C
.set SMF_SIGNATURE_OFFSET, 0x1300
.set SMF_SIGNATURE_CONST, 0x5f534d46 # '_SMF'
.set HILE_BIT_POS, 4
.set LE_BIT_POS, 63
.set MF_HRMOR_R1, 0xa64a397c
.set CLEAR_MSR_LE, 0xa407b57a
.set MT_SRR1, 0xa603bb7e
.set ADDI_R1_32, 0x20012138
.set MT_SRR0_R1, 0xa6033a7c
.set RFID, 0x2400004c
.set TRAP_LE, 0x0800e07f
.set MFMSR_R21, 0xa600a07e


.set SPR_SAVE_SCRATCH_REG, r0
.set SPR_DATA_REG, r1
Expand Down Expand Up @@ -285,6 +296,34 @@ _start:

_sreset_hndlr:

b big_endian_start

little_endian_start:
.long MF_HRMOR_R1
.long MFMSR_R21
.long CLEAR_MSR_LE
.long MT_SRR1
.long ADDI_R1_32
.long MT_SRR0_R1
.long RFID

#Note: below are instructions for swizzled machine code used above for
#LE core entering STOP
#mfspr r1, HRMOR
#mfmsr MSR_INIT_REG
#clrrdi MSR_INIT_REG, MSR_INIT_REG, 1
#mtsrr1 MSR_INIT_REG
#addi r1, r1, 288
#mtsrr0 r1
#rfid



big_endian_start:
mfspr SPR_DATA_REG, HID
li TEMP_REG1, 0
insrdi SPR_DATA_REG, TEMP_REG1, 1, HILE_BIT_POS
mtspr HID, SPR_DATA_REG # Cleared HILE bit position
mfmsr MSR_INIT_REG
ori MSR_INIT_REG, MSR_INIT_REG, MACHINE_CHECK_ENABLE_CONST # Set the ME bit
extrdi. MSR_SECURITY_ENABLE_REG, MSR_INIT_REG, 1, MSR_SECURITY_BIT # read Secure Bit (S) of MSR
Expand Down Expand Up @@ -782,7 +821,10 @@ cmpwi THREAD_ID_REG, 0 # if thread in question is 0, also,
bne save_restore_done # else saving of SPRs is done

save_core_spr:
addi SELF_RESTORE_ADDR_REG, CORE_SCOPE_RESTORE_ADDR_REG, 8
# 8B for mflr r30
# 32B for skipping HRMOR restore entry
# Self save should start at an offset 8B + 32B = 40B
addi SELF_RESTORE_ADDR_REG, CORE_SCOPE_RESTORE_ADDR_REG, 40
mtlr CORE_SELF_SAVE_BASE_ADDR
blrl

Expand Down
46 changes: 44 additions & 2 deletions import/chips/p9/procedures/utils/stopreg/p9_core_save_restore_routines.s
View file
Expand Up @@ -131,7 +131,7 @@
.set USRR0, 506
.set USRR1, 507
.set SMFCTRL, 511 # Ultravisor
.set HID0, 1008
.set HID, 1008
.set PIR, 1023

#--------------------SPR definition ends---------------------------------------
Expand Down Expand Up @@ -172,6 +172,17 @@
.set SELF_REST_VER_INFO_OFFSET, 0x1C
.set SMF_SIGNATURE_OFFSET, 0x1300
.set SMF_SIGNATURE_CONST, 0x5f534d46 # '_SMF'
.set HILE_BIT_POS, 4
.set LE_BIT_POS, 63
.set MF_HRMOR_R1, 0xa64a397c
.set CLEAR_MSR_LE, 0xa407b57a
.set MT_SRR1, 0xa603bb7e
.set ADDI_R1_32, 0x20012138
.set MT_SRR0_R1, 0xa6033a7c
.set RFID, 0x2400004c
.set TRAP_LE, 0x0800e07f
.set MFMSR_R21, 0xa600a07e


.set SPR_SAVE_SCRATCH_REG, r0
.set SPR_DATA_REG, r1
Expand Down Expand Up @@ -289,6 +300,34 @@ _start:

_sreset_hndlr:

b big_endian_start

little_endian_start:
.long MF_HRMOR_R1
.long MFMSR_R21
.long CLEAR_MSR_LE
.long MT_SRR1
.long ADDI_R1_32
.long MT_SRR0_R1
.long RFID

#Note: below are instructions for swizzled machine code used above for
#LE core entering STOP
#mfspr r1, HRMOR
#mfmsr MSR_INIT_REG
#clrrdi MSR_INIT_REG, MSR_INIT_REG, 1
#mtsrr1 MSR_INIT_REG
#addi r1, r1, 288
#mtsrr0 r1
#rfid



big_endian_start:
mfspr SPR_DATA_REG, HID
li TEMP_REG1, 0
insrdi SPR_DATA_REG, TEMP_REG1, 1, HILE_BIT_POS
mtspr HID, SPR_DATA_REG # Cleared HILE bit position
mfmsr MSR_INIT_REG
ori MSR_INIT_REG, MSR_INIT_REG, MACHINE_CHECK_ENABLE_CONST # Set the ME bit
extrdi. MSR_SECURITY_ENABLE_REG, MSR_INIT_REG, 1, MSR_SECURITY_BIT # read Secure Bit (S) of MSR
Expand Down Expand Up @@ -786,7 +825,10 @@ cmpwi THREAD_ID_REG, 0 # if thread in question is 0, also, save core SPRs
bne save_restore_done # else saving of SPRs is done

save_core_spr:
addi SELF_RESTORE_ADDR_REG, CORE_SCOPE_RESTORE_ADDR_REG, 8
# 8B for mflr r30
# 32B for skipping HRMOR restore entry
# Self save should start at an offset 8B + 32B = 40B
addi SELF_RESTORE_ADDR_REG, CORE_SCOPE_RESTORE_ADDR_REG, 40
mtlr CORE_SELF_SAVE_BASE_ADDR
blrl

Expand Down

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