This reverts the stop 1 commits

Change-Id: I351f8c6568540642eec0f95e6d7b3edea79e6a24
Original-Change-Id: Iddb6f734b8c05b97fc4d87268829ecb7af08fdf2
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40653
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Dev-Ready: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c

@@ -380,16 +380,18 @@ p9_cme_stop_entry()
             out32(CME_LCL_SICR_OR,  core_stop1 << SHIFT32(1));
             out32(CME_LCL_SICR_CLR, core_stop1 << SHIFT32(1));
 
-            // Removed: Do not want users to become accustomed to seeing Stop1 reflected in Stop History on DD1
-            //
-            //PK_TRACE("Update STOP history: in core stop level 1");
-            //scom_data.words.lower = 0;
-            //scom_data.words.upper = SSH_ACT_LV1_COMPLETE;
-            //CME_PUTSCOM(PPM_SSHSRC, core_stop1, scom_data.value);
-            //
+            PK_TRACE("Update STOP history: in core stop level 1");
+            scom_data.words.lower = 0;
+            scom_data.words.upper = SSH_ACT_LV1_COMPLETE;
+            CME_PUTSCOM(PPM_SSHSRC, core_stop1, scom_data.value);
 
             core = core & ~core_stop1;
 
+            if (!core)
+            {
+                break;
+            }
+
 #else
 
             // Nap should be done by hardware when auto_stop1 is enabled
@@ -401,6 +403,10 @@ p9_cme_stop_entry()
 
         }
 
+        //----------------------------------------------------------------------
+        PK_TRACE("+++++ +++++ STOP LEVEL 2 ENTRY +++++ +++++");
+        //----------------------------------------------------------------------
+
 #if HW405292_NDD1_PCBMUX_SAVIOR
 
         p9_cme_pcbmux_savior_prologue(core);
@@ -411,6 +417,7 @@ p9_cme_stop_entry()
         out32(CME_LCL_SICR_OR, core << SHIFT32(11));
 
         // Poll Infinitely for PCB Mux Grant
+        // MF: change watchdog timer in pk to ensure forward progress
         while((core & (in32(CME_LCL_SISR) >> SHIFT32(11))) != core);
 
         PK_TRACE("PCB Mux Granted on Core[%d]", core);
@@ -421,20 +428,6 @@ p9_cme_stop_entry()
 
 #endif
 
-#if HW386841_NDD1_DSL_STOP1_FIX
-
-        // exit after getting PCBMUX for Stop1 Workaround
-        if (!core)
-        {
-            break;
-        }
-
-#endif
-
-        //----------------------------------------------------------------------
-        PK_TRACE("+++++ +++++ STOP LEVEL 2 ENTRY +++++ +++++");
-        //----------------------------------------------------------------------
-
         // set target_level from pm_state for both cores or just one core
         target_level = (core == CME_MASK_C0) ? G_cme_stop_record.req_level[0] :
                        G_cme_stop_record.req_level[1];
@@ -571,6 +564,7 @@ p9_cme_stop_entry()
         while((lclr_data & core) != core);
 
         // Waits quiesce done for at least 512 core cycles
+        // MF: verify generate FCB otherwise math is wrong.
         PPE_WAIT_CORE_CYCLES(512)
 
         PK_TRACE_INF("SE.2B: Interfaces Quiesced");
@@ -699,6 +693,9 @@ p9_cme_stop_entry()
             PK_PANIC(CME_STOP_ENTRY_STOPCLK_FAILED);
         }
 
+        // MF: verify compiler generate single rlwmni
+        // MF: delay may be needed for stage latch to propagate thold
+
         PK_TRACE_INF("SE.2C: Core Clock Stopped");
 
         //==============================