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rbatraAustinIBMop-jenkins
rbatraAustinIBM
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PM: NACK disable and OCC notification
 Key_Cronus_Test=PM_REGRESS This commit fixes the issue where CME is told not to send NACKs to PGPE in case of prolonged droop condition, and as a consequence OCC is not told to suppress PM Reset. This results in requests from OCC in timeouts. To resolve, this issue CME sends a special NACK when bit to disable the regular NACK is set. In response, PGPE notifies OCC to suppress PM Reset Change-Id: I3cbc0420c91a3168c44106d0af7344162294a76a CQ: SW499739 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/101062 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Gregory S Still <stillgs@us.ibm.com> Reviewed-by: DAVID A KING <kingboy@us.ibm.com>
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‎import/chips/p9/common/pmlib/include/pstate_pgpe_cme_api.h

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
/* */
66
/* OpenPOWER HCODE Project */
77
/* */
8-
/* COPYRIGHT 2016,2019 */
8+
/* COPYRIGHT 2016,2020 */
99
/* [+] International Business Machines Corp. */
1010
/* */
1111
/* */
@@ -126,7 +126,8 @@ enum MESSAGEID_PCB_TYPE4_ACK_TYPES
126126
MSGID_PCB_TYPE4_QUAD_MGR_AVAILABLE = 3,
127127
MSGID_PCB_TYPE4_NACK_DROOP_PRESENT = 4,
128128
MSGID_PCB_TYPE4_SUSPEND_ENTRY_ACK = 5,
129-
MSGID_PCB_TYPE4_UNSUSPEND_ENTRY_ACK = 6
129+
MSGID_PCB_TYPE4_UNSUSPEND_ENTRY_ACK = 6,
130+
MSGID_PCB_TYPE4_NACK_DROOP_PRESENT_WITH_CSAR_SET = 7,
130131
};
131132

132133
enum DB0_CLIP_BCAST_FIELDS

‎import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
/* */
66
/* OpenPOWER HCODE Project */
77
/* */
8-
/* COPYRIGHT 2015,2019 */
8+
/* COPYRIGHT 2015,2020 */
99
/* [+] International Business Machines Corp. */
1010
/* */
1111
/* */
@@ -158,6 +158,7 @@ enum PM_CME_SCRATCH_DEFS
158158
//
159159
enum PM_CPPM_CSAR_DEFS
160160
{
161+
CPPM_CSAR_PGPE_ACK_FOR_NACK_ON_PROLONGED_DROOP_W_CSAR_SET = 26,
161162
CPPM_CSAR_FIT_HCODE_ERROR_INJECT = 27,
162163
CPPM_CSAR_ENABLE_PSTATE_REGISTRATION_INTERLOCK = 28,
163164
CPPM_CSAR_DISABLE_CME_NACK_ON_PROLONGED_DROOP = 29,

‎import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c

Lines changed: 25 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
/* */
66
/* OpenPOWER HCODE Project */
77
/* */
8-
/* COPYRIGHT 2015,2018 */
8+
/* COPYRIGHT 2015,2020 */
99
/* [+] International Business Machines Corp. */
1010
/* */
1111
/* */
@@ -107,6 +107,8 @@ uint32_t poll_dpll_stat()
107107
{
108108
data64_t data;
109109
uint32_t rc = 0;
110+
uint32_t ack;
111+
uint32_t pgpe_notified = 0;
110112

111113
// DPLL Modes
112114
// enable_fmin enable_fmax enable_jump
@@ -178,11 +180,29 @@ uint32_t poll_dpll_stat()
178180

179181
//If !CPPM_CSAR[DIS_NACK] AND (Elapsed Count > DROOP_POLL_COUNT), then prolonged
180182
//droop detected
181-
if (!(csar.value & BIT64(CPPM_CSAR_DISABLE_CME_NACK_ON_PROLONGED_DROOP)) &&
182-
elapsed > DROOP_POLL_COUNT)
183+
if ((elapsed > DROOP_POLL_COUNT) && (pgpe_notified == 0))
183184
{
184-
rc = 1; //Non-zero return code
185-
break;
185+
if (!(csar.value & BIT64(CPPM_CSAR_DISABLE_CME_NACK_ON_PROLONGED_DROOP)))
186+
{
187+
rc = 1; //Non-zero return code
188+
break;
189+
}
190+
else if ((csar.value & BIT64(CPPM_CSAR_DISABLE_CME_NACK_ON_PROLONGED_DROOP)) && (pgpe_notified == 0))
191+
{
192+
pgpe_notified = 1;
193+
PK_TRACE_INF("Nack on Droop disabled. Notifying PGPE about droop condition");
194+
ack = MSGID_PCB_TYPE4_NACK_DROOP_PRESENT_WITH_CSAR_SET;
195+
send_ack_to_pgpe(ack);
196+
197+
//Check for PGPE Ack
198+
CME_GETSCOM(CPPM_CSAR, G_cme_pstate_record.firstGoodCoreMask, csar.value);
199+
200+
while (!(csar.value & BIT64(CPPM_CSAR_PGPE_ACK_FOR_NACK_ON_PROLONGED_DROOP_W_CSAR_SET)))
201+
{
202+
//Spin until PGPE acks back
203+
CME_GETSCOM(CPPM_CSAR, G_cme_pstate_record.firstGoodCoreMask, csar.value);
204+
}
205+
}
186206
}
187207
}
188208
while(1);

‎import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c

Lines changed: 31 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
/* */
66
/* OpenPOWER HCODE Project */
77
/* */
8-
/* COPYRIGHT 2016,2019 */
8+
/* COPYRIGHT 2016,2020 */
99
/* [+] International Business Machines Corp. */
1010
/* */
1111
/* */
@@ -650,6 +650,7 @@ void p9_pgpe_wait_cme_db_ack(uint32_t quadAckExpect, uint32_t expectedAck)
650650
uint32_t q, c, ack;
651651
uint32_t opit4pr, opit4prQuad, opit4Clr = 0;
652652
ocb_opit4cn_t opit4cn;
653+
uint32_t quadNackWCSARSet = 0;
653654

654655
PK_TRACE_INF("DBW: AckExpect=0x%x, AckType=0x%x", quadAckExpect, expectedAck);
655656

@@ -700,6 +701,18 @@ void p9_pgpe_wait_cme_db_ack(uint32_t quadAckExpect, uint32_t expectedAck)
700701
PGPE_TRACE_AND_PANIC(PGPE_CME_UNEXPECTED_DB_ACK);
701702
}
702703

704+
//Clear our CPPM_CSAR if a nack with csar set was received from this quad
705+
if (quadNackWCSARSet & QUAD_MASK(q))
706+
{
707+
for (c = FIRST_CORE_FROM_QUAD(q); c < LAST_CORE_FROM_QUAD(q); c++)
708+
{
709+
if (G_pgpe_pstate_record.activeDB & CORE_MASK(c))
710+
{
711+
GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CSAR_CLR, c), BIT64(CPPM_CSAR_PGPE_ACK_FOR_NACK_ON_PROLONGED_DROOP_W_CSAR_SET));
712+
}
713+
}
714+
}
715+
703716
break;
704717

705718
case MSGID_PCB_TYPE4_NACK_DROOP_PRESENT: //0x4
@@ -708,6 +721,23 @@ void p9_pgpe_wait_cme_db_ack(uint32_t quadAckExpect, uint32_t expectedAck)
708721
G_pgpe_pstate_record.quadsNACKed |= QUAD_MASK(q);
709722
break;
710723

724+
case MSGID_PCB_TYPE4_NACK_DROOP_PRESENT_WITH_CSAR_SET: //0x7
725+
PK_TRACE_INF("DBW: Nack woth CSAR Set. Setting OCCLFG[PM_RESET_SUPPRESS] ");
726+
out32(G_OCB_OCCFLG_OR, BIT32(PGPE_PM_RESET_SUPPRESS));//Set OCCFLG[PM_RESET_SUPPRESS]
727+
quadNackWCSARSet |= QUAD_MASK(q);
728+
quadAckExpect |= QUAD_MASK(q); //Add it back to the expect because CME will send another ACK when the droop has subsided
729+
730+
//Notify CME that PGPE has seen this ACK
731+
for (c = FIRST_CORE_FROM_QUAD(q); c < LAST_CORE_FROM_QUAD(q); c++)
732+
{
733+
if (G_pgpe_pstate_record.activeDB & CORE_MASK(c))
734+
{
735+
GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CSAR_OR, c), BIT64(CPPM_CSAR_PGPE_ACK_FOR_NACK_ON_PROLONGED_DROOP_W_CSAR_SET));
736+
}
737+
}
738+
739+
break;
740+
711741
//Note this includes MSGID_PCB_TYPE4_QUAD_MGR_AVAILABLE(0x3)
712742
//and other undefined encoding
713743
default:

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