Skip to content

Commit d0ee996

Browse files
prasrangop-jenkins
prasrang
authored and
op-jenkins
committed
PFET: Re-verify the pfet header error in FIT interrupt handler
 - We found there was a timing issue, when core is tried to wakeup and in poweron process we were seeing pfet header issue that gets caught in fit interrupt handler which can be a false error ,because fit interrupt comes regularly and which is high priority and it might detec bad pfet, even though hardware still under process of poweron. Change-Id: Ib74e0369e3db2acd53819e210a6389859c888ec2 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/106593 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com> Reviewed-by: Gregory S Still <stillgs@us.ibm.com> Reviewed-by: NAREN A DEVAIAH <naren.devaiah@in.ibm.com>
1 parent 8921f64 commit d0ee996

File tree

5 files changed

+93
-74
lines changed

5 files changed

+93
-74
lines changed

‎import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c

Lines changed: 23 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -103,8 +103,18 @@ void fit_handler()
103103
( ( ( scom_data.words.upper & BIT32(0) ) == 0 ) &&
104104
( ( scom_data.words.upper & BIT32(1) ) == 0 ) ) )
105105
{
106-
CME_PUTSCOM_NOP(CPPM_CPMMR_OR, CME_MASK_C0, BIT64(5));
107-
PK_PANIC(CME_BAD_PFET);
106+
PPE_WAIT_CORE_CYCLES(512)
107+
CME_GETSCOM(PPM_PFSNS, CME_MASK_C0, scom_data);
108+
109+
if( ( ( ( scom_data.words.upper & BIT32(0) ) == 1 ) &&
110+
( ( scom_data.words.upper & BIT32(1) ) == 1 ) ) ||
111+
( ( ( scom_data.words.upper & BIT32(0) ) == 0 ) &&
112+
( ( scom_data.words.upper & BIT32(1) ) == 0 ) ) )
113+
{
114+
115+
CME_PUTSCOM_NOP(CPPM_CPMMR_OR, CME_MASK_C0, BIT64(5));
116+
PK_PANIC(CME_BAD_PFET);
117+
}
108118
}
109119

110120
CME_GETSCOM(PPM_PFSNS, CME_MASK_C1, scom_data);
@@ -114,8 +124,17 @@ void fit_handler()
114124
( ( ( scom_data.words.upper & BIT32(0) ) == 0 ) &&
115125
( ( scom_data.words.upper & BIT32(1) ) == 0 ) ) )
116126
{
117-
CME_PUTSCOM_NOP(CPPM_CPMMR_OR, CME_MASK_C1, BIT64(6));
118-
PK_PANIC(CME_BAD_PFET);
127+
PPE_WAIT_CORE_CYCLES(512)
128+
CME_GETSCOM(PPM_PFSNS, CME_MASK_C1, scom_data);
129+
130+
if( ( ( ( scom_data.words.upper & BIT32(0) ) == 1 ) &&
131+
( ( scom_data.words.upper & BIT32(1) ) == 1 ) ) ||
132+
( ( ( scom_data.words.upper & BIT32(0) ) == 0 ) &&
133+
( ( scom_data.words.upper & BIT32(1) ) == 0 ) ) )
134+
{
135+
CME_PUTSCOM_NOP(CPPM_CPMMR_OR, CME_MASK_C1, BIT64(6));
136+
PK_PANIC(CME_BAD_PFET);
137+
}
119138
}
120139

121140
CME_GETSCOM_OR(CPPM_CSAR, CME_MASK_BC, scom_data.value);

‎import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ void p9_cme_pstate_intercme_msg_handler(void)
6363

6464
void p9_cme_pstate_sibling_lock_and_intercme_protocol(INTERCME_MSG_LOCK_ACTION intercme_msg_lock_action)
6565
{
66-
PK_TRACE_DBG("SIBL: Enter");
66+
PK_TRACE_INF("SIBL: Enter");
6767
uint32_t msg;
6868

6969
if (intercme_msg_lock_action == INTERCME_MSG_LOCK_WAIT_ON_RECV)
@@ -101,7 +101,7 @@ void p9_cme_pstate_process_db0_sibling()
101101
//writes same value for both cores
102102
CME_GETSCOM(CPPM_CMEDB0, G_cme_pstate_record.firstGoodCoreMask, dbData.value);
103103

104-
PK_TRACE_DBG("INTER0: Enter");
104+
PK_TRACE_INF("INTER0: Enter");
105105

106106
dbQuadInfo = (dbData.value >> (in32(G_CME_LCL_SRTCH0) &
107107
(BITS32(CME_SCRATCH_LOCAL_PSTATE_IDX_START, CME_SCRATCH_LOCAL_PSTATE_IDX_LENGTH)
@@ -110,7 +110,7 @@ void p9_cme_pstate_process_db0_sibling()
110110

111111
if(dbData.fields.cme_message_number0 == MSGID_DB0_START_PSTATE_BROADCAST)
112112
{
113-
PK_TRACE_INF("INTER0: DB0 Start");
113+
//PK_TRACE_INF("INTER0: DB0 Start");
114114

115115
G_cme_pstate_record.quadPstate = dbQuadInfo;
116116
G_cme_pstate_record.globalPstate = dbBit8_15;
@@ -131,14 +131,14 @@ void p9_cme_pstate_process_db0_sibling()
131131
else if((dbData.fields.cme_message_number0 == MSGID_DB0_GLOBAL_ACTUAL_BROADCAST) ||
132132
(dbData.fields.cme_message_number0 == MSGID_DB0_DB3_PAYLOAD))
133133
{
134-
PK_TRACE_INF("INTER0: DB0 GlbBcast");
134+
//PK_TRACE_INF("INTER0: DB0 GlbBcast");
135135
G_cme_pstate_record.quadPstate = dbQuadInfo;
136136
G_cme_pstate_record.globalPstate = dbBit8_15;
137137
p9_cme_pstate_pmsr_updt();
138138
}
139139
else if(dbData.fields.cme_message_number0 == MSGID_DB0_CLIP_BROADCAST)
140140
{
141-
PK_TRACE_INF("INTER0: DB0 Clip");
141+
//PK_TRACE_INF("INTER0: DB0 Clip");
142142

143143
if (dbBit8_15 == DB0_CLIP_BCAST_TYPE_PMIN)
144144
{
@@ -153,7 +153,7 @@ void p9_cme_pstate_process_db0_sibling()
153153
}
154154
else if(dbData.fields.cme_message_number0 == MSGID_DB0_STOP_PSTATE_BROADCAST)
155155
{
156-
PK_TRACE_INF("INTER0: DB0 Stop");
156+
//PK_TRACE_INF("INTER0: DB0 Stop");
157157
out32_sh(CME_LCL_EIMR_OR, (BITS64SH(34, 2)));//Disable PMCR0/1
158158
g_eimr_override |= BITS64(34, 2);
159159

@@ -168,7 +168,7 @@ void p9_cme_pstate_process_db0_sibling()
168168
}
169169
else if(dbData.fields.cme_message_number0 == MSGID_DB0_PMSR_UPDT)
170170
{
171-
PK_TRACE_INF("INTER0: DB0 PMSR Updt");
171+
//PK_TRACE_INF("INTER0: DB0 PMSR Updt");
172172

173173
switch(dbBit8_15)
174174
{

‎import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -82,12 +82,12 @@ int send_pig_packet(uint64_t data, uint32_t coreMask)
8282
}
8383
while ((((ppm_pig_t)data_tmp).fields.pending_source & 0x1));
8484

85-
PK_TRACE_INF("send pig core=0x%x, data=0x%08x%08x", coreMask, data >> 32, data);
85+
//PK_TRACE_INF("send pig core=0x%x, data=0x%08x%08x", coreMask, data >> 32, data);
8686

8787
// Send PIG packet
8888
CME_PUTSCOM(PPM_PIG, coreMask, data);
89-
PK_TRACE_DBG("CME: Sending PIG[%x] at core[%x]",
90-
(uint32_t)(data >> 32), coreMask);
89+
//PK_TRACE_DBG("CME: Sending PIG[%x] at core[%x]",
90+
// (uint32_t)(data >> 32), coreMask);
9191

9292
pk_critical_section_exit(&ctx);
9393

@@ -127,7 +127,7 @@ uint32_t poll_dpll_stat()
127127
// DPLL Mode 2
128128
if(!(in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_VDM_OPERABLE)))
129129
{
130-
PK_TRACE_INF("Poll on DPLL_STAT[freq_change=0]");
130+
//PK_TRACE_INF("Poll on DPLL_STAT[freq_change=0]");
131131

132132
// ... to indicate that the DPLL is safely either at the new frequency
133133
// or in droop protection below the new frequency
@@ -140,7 +140,7 @@ uint32_t poll_dpll_stat()
140140
else
141141
// DPLL Mode 3
142142
{
143-
PK_TRACE_INF("Poll on DPLL_STAT[update_complete=1]");
143+
//PK_TRACE_INF("Poll on DPLL_STAT[update_complete=1]");
144144
// ... to indicate that the DPLL has sampled the newly requested
145145
// frequency into its internal registers as a target,
146146
// but may not yet be there
@@ -190,7 +190,7 @@ uint32_t poll_dpll_stat()
190190
else if ((csar.value & BIT64(CPPM_CSAR_DISABLE_CME_NACK_ON_PROLONGED_DROOP)) && (pgpe_notified == 0))
191191
{
192192
pgpe_notified = 1;
193-
PK_TRACE_INF("Nack on Droop disabled. Notifying PGPE about droop condition");
193+
//PK_TRACE_INF("Nack on Droop disabled. Notifying PGPE about droop condition");
194194
ack = MSGID_PCB_TYPE4_NACK_DROOP_PRESENT_WITH_CSAR_SET;
195195
send_ack_to_pgpe(ack);
196196

@@ -293,7 +293,7 @@ void intercme_msg_send(uint32_t msg, INTERCME_MSG_TYPE type)
293293
{
294294
out32(G_CME_LCL_ICSR, (msg << 4) | type);
295295

296-
PK_TRACE_DBG("imt send | msg=%08x", ((msg << 4) | type));
296+
//PK_TRACE_DBG("imt send | msg=%08x", ((msg << 4) | type));
297297

298298
// Block on ack from companion CME
299299
while(!(in32(G_CME_LCL_EISR) & BIT32(30))) {}
@@ -307,7 +307,7 @@ void intercme_msg_recv(uint32_t* msg, INTERCME_MSG_TYPE type)
307307
while(!(in32(G_CME_LCL_EISR) & BIT32(29))) {}
308308

309309
*msg = in32(G_CME_LCL_ICRR);
310-
PK_TRACE_DBG("imt recv | msg=%08x", *msg);
310+
//PK_TRACE_DBG("imt recv | msg=%08x", *msg);
311311

312312
if(*msg & type)
313313
{
@@ -393,7 +393,7 @@ uint32_t p9_cme_resclk_get_index(uint32_t pstate)
393393
// disabled
394394
while((pstate > G_lppb->resclk.resclk_freq[--i]) && (i > 0)) {}
395395

396-
PK_TRACE_DBG("resclk_idx[i=%d]=%d", i, G_lppb->resclk.resclk_index[i]);
396+
//PK_TRACE_DBG("resclk_idx[i=%d]=%d", i, G_lppb->resclk.resclk_index[i]);
397397
return((uint32_t)G_lppb->resclk.resclk_index[i]);
398398
}
399399
#endif//USE_CME_RESCLK_FEATURE
@@ -410,7 +410,7 @@ void p9_cme_core_stop_analog_control(uint32_t core_mask, ANALOG_CONTROL enable)
410410

411411
if(enable)
412412
{
413-
PK_TRACE_INF("resclk | enabling resclks");
413+
//PK_TRACE_INF("resclk | enabling resclks");
414414

415415
if(core_mask == CME_MASK_C0)
416416
{
@@ -434,7 +434,7 @@ void p9_cme_core_stop_analog_control(uint32_t core_mask, ANALOG_CONTROL enable)
434434
}
435435
else
436436
{
437-
PK_TRACE_INF("resclk | disabling resclks");
437+
//PK_TRACE_INF("resclk | disabling resclks");
438438
// 1) copy QACCR[0:12] into CACCR[0:12], with CACCR[13:14]=0b00,
439439
// to switch away from common control. QACCR will already be set
440440
// to a value corresponding to the current quad Pstate
@@ -458,15 +458,15 @@ void p9_cme_core_stop_analog_control(uint32_t core_mask, ANALOG_CONTROL enable)
458458
{
459459
if(enable)
460460
{
461-
PK_TRACE_INF("vdm | enabling vdms");
461+
//PK_TRACE_INF("vdm | enabling vdms");
462462
// Clear Disable
463463
// (Poweron is set earlier in Stop4 Exit flow
464464
// due to delay required between poweron and enable)
465465
CME_PUTSCOM(PPM_VDMCR_CLR, core_mask, BIT64(1));
466466
}
467467
else
468468
{
469-
PK_TRACE_INF("vdm | disabling vdms");
469+
//PK_TRACE_INF("vdm | disabling vdms");
470470
// Set Disable (Poweron is cleared in Stop4 Entry)
471471
CME_PUTSCOM(PPM_VDMCR_OR, core_mask, BIT64(1));
472472
}
@@ -643,7 +643,7 @@ inline uint32_t update_vdm_jump_values_in_dpll(uint32_t pstate, uint32_t region)
643643
// Clear jump enable (drop to Mode 2)
644644
nonatomic_ippm_write(QPPM_DPLL_CTRL_CLR, BIT64(1));
645645
// Poll for lock
646-
PK_TRACE_INF("Poll on DPLL_STAT[block_active|lock]");
646+
//PK_TRACE_INF("Poll on DPLL_STAT[block_active|lock]");
647647

648648
// ... to indicate that the DPLL is safely either at the new frequency
649649
// or in droop protection below the new frequency
@@ -816,9 +816,9 @@ void p9_cme_resclk_update(ANALOG_TARGET target, uint32_t next_idx, uint32_t curr
816816
uint64_t val;
817817
int32_t step;
818818

819-
PK_TRACE_DBG("resclk | target=%08x", (uint32_t)target);
820-
PK_TRACE_DBG("resclk | curr_idx=%d", curr_idx);
821-
PK_TRACE_DBG("resclk | next_idx=%d", next_idx);
819+
//PK_TRACE_DBG("resclk | target=%08x", (uint32_t)target);
820+
//PK_TRACE_DBG("resclk | curr_idx=%d", curr_idx);
821+
//PK_TRACE_DBG("resclk | next_idx=%d", next_idx);
822822

823823
// Determine the step polarity, step is not used if curr_idx == next_idx
824824
if(curr_idx < next_idx)

0 commit comments

Comments
 (0)