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24x7: Added Alink PMU & fix for defect SW430218
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Change-Id: Ia7a1a3706ebaf2bf300e3f875bdbfde0621c83ea
CQ:SW433340
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59632
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
(cherry picked from commit 074010f)
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61244
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@sumitk56 @marthabroyles
sumitk56 authored and marthabroyles committed Jun 28, 2018
1 parent 6303307 commit 3efcf7c
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Showing 2 changed files with 161 additions and 13 deletions.
123 changes: 117 additions & 6 deletions src/occ_gpe1/gpe1_24x7.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -108,11 +108,11 @@ void gpe_24x7(ipc_msg_t* cmd, void* arg)
* [48:63] - Reserved
**/
uint64_t VERSION = 0;
static uint64_t ver_major = 0x1;
static uint64_t ver_major = 0x2;
static uint64_t ver_minor = 0x0;
static uint64_t ver_bugfix = 0x0;
static uint64_t ver_day = 0x27; // Day: 27
static uint64_t ver_month = 0x04; // Month: 04
static uint64_t ver_day = 0x31; // Day: 27
static uint64_t ver_month = 0x05; // Month: 04
static uint64_t ver_year = 0x2018; // Year:2018

VERSION |= (ver_major << 60);
Expand Down Expand Up @@ -479,6 +479,7 @@ void gpe_24x7(ipc_msg_t* cmd, void* arg)
**/
void configure_pmu(uint8_t state, uint64_t speed)
{//write the configuration SCOMs for all pmus.
uint64_t temp;
int i,start = (state - 1) * 16,end = state * 16;
static volatile uint64_t* L_conf_last = (uint64_t*) (DBG_CONF_OFFSET | PBA_ENABLE);
static volatile uint64_t* L_DBG_0 = (uint64_t*) (DBG_0 | PBA_ENABLE);
Expand Down Expand Up @@ -572,13 +573,35 @@ void configure_pmu(uint8_t state, uint64_t speed)
//1.for speeds till 8ms- 8 bit prescale
if((speed == CNTL_SPEED_1MS)||(speed == CNTL_SPEED_2MS)||(speed == CNTL_SPEED_4MS)||(speed == CNTL_SPEED_8MS))
{
putscom_abs(G_PMU_CONFIGS_8[i][0], G_PMU_CONFIGS_8[i][1]);
// Fix for defect SW430218 - 24x7 to touch only XTS Config2 bits [0:47]
if ( G_PMU_CONFIGS_8[i][0] == 0x5011645 )
{
getscom_abs(G_PMU_CONFIGS_8[i][0], &temp);
temp &= (0xFFFF);
temp |= G_PMU_CONFIGS_8[i][1];
putscom_abs(G_PMU_CONFIGS_8[i][0], temp);
}
else
{
putscom_abs(G_PMU_CONFIGS_8[i][0], G_PMU_CONFIGS_8[i][1]);
}
*L_conf_last = (uint64_t)i;
}
//2.for all speeds above 8 ms till 2s - 16bit prescale
else
{
putscom_abs(G_PMU_CONFIGS_16[i][0], G_PMU_CONFIGS_16[i][1]);
// Fix for defect SW430218 - 24x7 to touch only XTS Config2 bits [0:47]
if ( G_PMU_CONFIGS_16[i][0] == 0x5011645 )
{
getscom_abs(G_PMU_CONFIGS_16[i][0], &temp);
temp &= (0xFFFF);
temp |= G_PMU_CONFIGS_16[i][1];
putscom_abs(G_PMU_CONFIGS_16[i][0], temp);
}
else
{
putscom_abs(G_PMU_CONFIGS_16[i][0], G_PMU_CONFIGS_16[i][1]);
}
*L_conf_last = (uint64_t)i;
}
}
Expand All @@ -594,6 +617,7 @@ void post_pmu_events(int grp)
static int L_phb_events =0;
static volatile uint64_t* L_DBG_GRP = (uint64_t*) (DBG_GRP_OFFSET | PBA_ENABLE);
static volatile uint64_t* L_DBG_UNIT = (uint64_t*) (DBG_UNIT_OFFSET | PBA_ENABLE);
static bool L_X_A_LINKS_flag = false;
//static volatile uint64_t* L_DBG_4 = (uint64_t*) (DBG_4 | PBA_ENABLE);
//static volatile uint64_t* L_DBG_5 = (uint64_t*) (DBG_5 | PBA_ENABLE);
//static volatile uint64_t* L_DBG_6 = (uint64_t*) (DBG_6 | PBA_ENABLE);
Expand Down Expand Up @@ -658,7 +682,11 @@ void post_pmu_events(int grp)
post_addr = (uint64_t*) (POST_OFFSET_DBG1T | PBA_ENABLE);
*post_addr = INC_UPD_COUNT;
break;
case G2://XLINKS and NX. Read scoms based on availability.
case G2://XLINKS,NX and ALINKS. Read scoms based on availability.
if (L_X_A_LINKS_flag) //Here do xlink-[0:2] and nx
{
L_X_A_LINKS_flag = false;

*L_DBG_GRP = 2;
post_addr = (uint64_t*) (POST_OFFSET_G2H | PBA_ENABLE);
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
Expand Down Expand Up @@ -742,6 +770,89 @@ void post_pmu_events(int grp)
}
post_addr = (uint64_t*) (POST_OFFSET_G2T | PBA_ENABLE);
*post_addr = INC_UPD_COUNT;
}
else //Here do alink [0:3]
{
L_X_A_LINKS_flag = true;

if ((G_CUR_UAV & MASK_ALNK0) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 1;
post_addr = (uint64_t*) (POST_OFFSET_G2_A0 | PBA_ENABLE);
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
getscom_abs(G_PMULETS_2_2a[0], &u3.pmulet);
for(j=0; j<4; j++)
{
*post_addr = (uint64_t)u3.ev.e[j];
post_addr++;
}
getscom_abs(G_PMULETS_2_2a[1], &u3.pmulet);
for(j=0; j<4; j++)
{
*post_addr = (uint64_t)u3.ev.e[j];
post_addr++;
}
}
if ((G_CUR_UAV & MASK_ALNK1) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 1;
post_addr = (uint64_t*) (POST_OFFSET_G2_A1 | PBA_ENABLE);
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
getscom_abs(G_PMULETS_2_2b[0], &u3.pmulet);
for(j=0; j<4; j++)
{
*post_addr = (uint64_t)u3.ev.e[j];
post_addr++;
}
getscom_abs(G_PMULETS_2_2b[1], &u3.pmulet);
for(j=0; j<4; j++)
{
*post_addr = (uint64_t)u3.ev.e[j];
post_addr++;
}
}

if ((G_CUR_UAV & MASK_ALNK2) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 1;
post_addr = (uint64_t*) (POST_OFFSET_G2_A2 | PBA_ENABLE);
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
getscom_abs(G_PMULETS_2_2c[0], &u3.pmulet);
for(j=0; j<4; j++)
{
*post_addr = (uint64_t)u3.ev.e[j];
post_addr++;
}
getscom_abs(G_PMULETS_2_2c[1], &u3.pmulet);
for(j=0; j<4; j++)
{
*post_addr = (uint64_t)u3.ev.e[j];
post_addr++;
}
}
if ((G_CUR_UAV & MASK_ALNK3) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 1;
post_addr = (uint64_t*) (POST_OFFSET_G2_A3 | PBA_ENABLE);
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
getscom_abs(G_PMULETS_2_2d[0], &u3.pmulet);
for(j=0; j<4; j++)
{
*post_addr = (uint64_t)u3.ev.e[j];
post_addr++;
}
getscom_abs(G_PMULETS_2_2d[1], &u3.pmulet);
for(j=0; j<4; j++)
{
*post_addr = (uint64_t)u3.ev.e[j];
post_addr++;
}
}
}
break;
case G3://NVLINKS -NTL,ATS,XTS
*L_DBG_GRP = 3;
Expand Down
51 changes: 44 additions & 7 deletions src/occ_gpe1/gpe1_24x7.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,11 +28,11 @@

//PMU config table defined below.
//------------------------------
#define TOTAL_CONFIGS 60
#define TOTAL_CONFIGS 61
#define TOTAL_POSTINGS 238
#define INC_UPD_COUNT 1

#define TOTAL_CONFIG_SCOMS 60
#define TOTAL_CONFIG_SCOMS 61
#define TOTAL_COUNTER_SCOMS 71

#define MAX_32 4294967295ULL
Expand Down Expand Up @@ -77,7 +77,7 @@ uint64_t G_PMU_CONFIGS_8[][2] =
{0x50108be, 0x00005345755b6000},//port2,3//26
{0x50108bf, 0x000e800000000000},//port2,3//27
//xlinks//
{0x501341a, 0xff015daa15555000},//all xlinks//28
{0x501341a, 0xff115daa15555000},//all xlinks//28
//nx//
{0x20110a6, 0xcaa0000080000000},//29
{0x20110a9, 0xcaa0492480000000},//30
Expand Down Expand Up @@ -113,7 +113,9 @@ uint64_t G_PMU_CONFIGS_8[][2] =
{0x4010816, 0x6000000000000000},//CAPP02//56
{0x4010824, 0x8058914202000000},//CAPP02//57
{0x4010822, 0x1000000000000000},//CAPP02//58
{0x4010817, 0x0000000000000000} //CAPP02//59
{0x4010817, 0x0000000000000000},//CAPP02//59
//alinks//
{0x501381a, 0xff115daa05555000}//all alinks//60
};

uint64_t G_PMU_CONFIGS_16[][2] =
Expand Down Expand Up @@ -150,7 +152,7 @@ uint64_t G_PMU_CONFIGS_16[][2] =
{0x50108be, 0x00005345755b6000},//port2,3//26
{0x50108bf, 0x000e800000000000},//port2,3//27
//xlinks
{0x501341a, 0xff015d5515555000},//all xlinks//28
{0x501341a, 0xff115d5515555000},//all xlinks//28
//nx
{0x20110a6, 0xc550000080000000},//29
{0x20110a9, 0xc550492480000000},//30
Expand Down Expand Up @@ -186,7 +188,9 @@ uint64_t G_PMU_CONFIGS_16[][2] =
{0x4010816, 0x6000000000000000},//CAPP02//56
{0x4010824, 0x803850c102000000},//CAPP02//57
{0x4010822, 0x1000000000000000},//CAPP02//58
{0x4010817, 0x0000000000000000} //CAPP02//59
{0x4010817, 0x0000000000000000},//CAPP02//59
//alinks//
{0x501341a, 0xff115d5505555000}//all alinks//60
};


Expand Down Expand Up @@ -337,6 +341,31 @@ uint64_t G_PMULETS_7[] =
0x4010825//6//70
};

//Alink - fips920
uint64_t G_PMULETS_2_2a[] =
{//Alink0
0x501381b,//0-even
0x501381c,//1-odd
};

uint64_t G_PMULETS_2_2b[] =
{//Alink1
0x501381d,//2-even
0x501381e,//3-odd
};

uint64_t G_PMULETS_2_2c[] =
{//Alink2
0x501381f,//4-even
0x5013820,//5-odd
};

uint64_t G_PMULETS_2_2d[] =
{//Alink3
0x5013821,//6-even
0x5013822,//7-odd
};

/**
* Groups
**/
Expand Down Expand Up @@ -375,7 +404,7 @@ enum
POST_OFFSET_G2_4 = 0x001801D8,
POST_OFFSET_G2T = 0x00180218,

// Group G3 - INTL
// Group G3 - NTL
POST_OFFSET_G3H = 0x00180220,
POST_OFFSET_G3_1 = 0x00180228,
POST_OFFSET_G3_2 = 0x00180248,
Expand Down Expand Up @@ -404,6 +433,10 @@ enum
POST_OFFSET_G5_4 = 0x00180490,
POST_OFFSET_G5T = 0x00180548,

// Group G2 - ALINK 0-1 - part of G5 MBA0-3
POST_OFFSET_G2_A0 = 0x001804A8,
POST_OFFSET_G2_A1 = 0x001804E8,

// Group G6 - MBA 4-7
POST_OFFSET_G6H = 0x00180550,
POST_OFFSET_G6_1 = 0x00180558,
Expand All @@ -412,6 +445,10 @@ enum
POST_OFFSET_G6_4 = 0x001805A0,
POST_OFFSET_G6T = 0x00180658,

// Group G2 - ALINK 2-3 - part of G5 MBA4-7
POST_OFFSET_G2_A2 = 0x001805B8,
POST_OFFSET_G2_A3 = 0x001805F8,

// Group G7 - NPCQ/CAPP
POST_OFFSET_G7H = 0x00180660,
POST_OFFSET_G7_1 = 0x00180668,
Expand Down

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