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sumitk56marthabroyles
sumitk56
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marthabroyles
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24x7: Added Alink PMU & fix for defect SW430218
Change-Id: Ia7a1a3706ebaf2bf300e3f875bdbfde0621c83ea CQ:SW433340 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59632 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> (cherry picked from commit 074010f) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61244
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‎src/occ_gpe1/gpe1_24x7.c

Lines changed: 117 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -108,11 +108,11 @@ void gpe_24x7(ipc_msg_t* cmd, void* arg)
108108
* [48:63] - Reserved
109109
**/
110110
uint64_t VERSION = 0;
111-
static uint64_t ver_major = 0x1;
111+
static uint64_t ver_major = 0x2;
112112
static uint64_t ver_minor = 0x0;
113113
static uint64_t ver_bugfix = 0x0;
114-
static uint64_t ver_day = 0x27; // Day: 27
115-
static uint64_t ver_month = 0x04; // Month: 04
114+
static uint64_t ver_day = 0x31; // Day: 27
115+
static uint64_t ver_month = 0x05; // Month: 04
116116
static uint64_t ver_year = 0x2018; // Year:2018
117117

118118
VERSION |= (ver_major << 60);
@@ -479,6 +479,7 @@ void gpe_24x7(ipc_msg_t* cmd, void* arg)
479479
**/
480480
void configure_pmu(uint8_t state, uint64_t speed)
481481
{//write the configuration SCOMs for all pmus.
482+
uint64_t temp;
482483
int i,start = (state - 1) * 16,end = state * 16;
483484
static volatile uint64_t* L_conf_last = (uint64_t*) (DBG_CONF_OFFSET | PBA_ENABLE);
484485
static volatile uint64_t* L_DBG_0 = (uint64_t*) (DBG_0 | PBA_ENABLE);
@@ -572,13 +573,35 @@ void configure_pmu(uint8_t state, uint64_t speed)
572573
//1.for speeds till 8ms- 8 bit prescale
573574
if((speed == CNTL_SPEED_1MS)||(speed == CNTL_SPEED_2MS)||(speed == CNTL_SPEED_4MS)||(speed == CNTL_SPEED_8MS))
574575
{
575-
putscom_abs(G_PMU_CONFIGS_8[i][0], G_PMU_CONFIGS_8[i][1]);
576+
// Fix for defect SW430218 - 24x7 to touch only XTS Config2 bits [0:47]
577+
if ( G_PMU_CONFIGS_8[i][0] == 0x5011645 )
578+
{
579+
getscom_abs(G_PMU_CONFIGS_8[i][0], &temp);
580+
temp &= (0xFFFF);
581+
temp |= G_PMU_CONFIGS_8[i][1];
582+
putscom_abs(G_PMU_CONFIGS_8[i][0], temp);
583+
}
584+
else
585+
{
586+
putscom_abs(G_PMU_CONFIGS_8[i][0], G_PMU_CONFIGS_8[i][1]);
587+
}
576588
*L_conf_last = (uint64_t)i;
577589
}
578590
//2.for all speeds above 8 ms till 2s - 16bit prescale
579591
else
580592
{
581-
putscom_abs(G_PMU_CONFIGS_16[i][0], G_PMU_CONFIGS_16[i][1]);
593+
// Fix for defect SW430218 - 24x7 to touch only XTS Config2 bits [0:47]
594+
if ( G_PMU_CONFIGS_16[i][0] == 0x5011645 )
595+
{
596+
getscom_abs(G_PMU_CONFIGS_16[i][0], &temp);
597+
temp &= (0xFFFF);
598+
temp |= G_PMU_CONFIGS_16[i][1];
599+
putscom_abs(G_PMU_CONFIGS_16[i][0], temp);
600+
}
601+
else
602+
{
603+
putscom_abs(G_PMU_CONFIGS_16[i][0], G_PMU_CONFIGS_16[i][1]);
604+
}
582605
*L_conf_last = (uint64_t)i;
583606
}
584607
}
@@ -594,6 +617,7 @@ void post_pmu_events(int grp)
594617
static int L_phb_events =0;
595618
static volatile uint64_t* L_DBG_GRP = (uint64_t*) (DBG_GRP_OFFSET | PBA_ENABLE);
596619
static volatile uint64_t* L_DBG_UNIT = (uint64_t*) (DBG_UNIT_OFFSET | PBA_ENABLE);
620+
static bool L_X_A_LINKS_flag = false;
597621
//static volatile uint64_t* L_DBG_4 = (uint64_t*) (DBG_4 | PBA_ENABLE);
598622
//static volatile uint64_t* L_DBG_5 = (uint64_t*) (DBG_5 | PBA_ENABLE);
599623
//static volatile uint64_t* L_DBG_6 = (uint64_t*) (DBG_6 | PBA_ENABLE);
@@ -658,7 +682,11 @@ void post_pmu_events(int grp)
658682
post_addr = (uint64_t*) (POST_OFFSET_DBG1T | PBA_ENABLE);
659683
*post_addr = INC_UPD_COUNT;
660684
break;
661-
case G2://XLINKS and NX. Read scoms based on availability.
685+
case G2://XLINKS,NX and ALINKS. Read scoms based on availability.
686+
if (L_X_A_LINKS_flag) //Here do xlink-[0:2] and nx
687+
{
688+
L_X_A_LINKS_flag = false;
689+
662690
*L_DBG_GRP = 2;
663691
post_addr = (uint64_t*) (POST_OFFSET_G2H | PBA_ENABLE);
664692
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
@@ -742,6 +770,89 @@ void post_pmu_events(int grp)
742770
}
743771
post_addr = (uint64_t*) (POST_OFFSET_G2T | PBA_ENABLE);
744772
*post_addr = INC_UPD_COUNT;
773+
}
774+
else //Here do alink [0:3]
775+
{
776+
L_X_A_LINKS_flag = true;
777+
778+
if ((G_CUR_UAV & MASK_ALNK0) > 0)
779+
{
780+
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
781+
*L_DBG_UNIT = 1;
782+
post_addr = (uint64_t*) (POST_OFFSET_G2_A0 | PBA_ENABLE);
783+
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
784+
getscom_abs(G_PMULETS_2_2a[0], &u3.pmulet);
785+
for(j=0; j<4; j++)
786+
{
787+
*post_addr = (uint64_t)u3.ev.e[j];
788+
post_addr++;
789+
}
790+
getscom_abs(G_PMULETS_2_2a[1], &u3.pmulet);
791+
for(j=0; j<4; j++)
792+
{
793+
*post_addr = (uint64_t)u3.ev.e[j];
794+
post_addr++;
795+
}
796+
}
797+
if ((G_CUR_UAV & MASK_ALNK1) > 0)
798+
{
799+
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
800+
*L_DBG_UNIT = 1;
801+
post_addr = (uint64_t*) (POST_OFFSET_G2_A1 | PBA_ENABLE);
802+
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
803+
getscom_abs(G_PMULETS_2_2b[0], &u3.pmulet);
804+
for(j=0; j<4; j++)
805+
{
806+
*post_addr = (uint64_t)u3.ev.e[j];
807+
post_addr++;
808+
}
809+
getscom_abs(G_PMULETS_2_2b[1], &u3.pmulet);
810+
for(j=0; j<4; j++)
811+
{
812+
*post_addr = (uint64_t)u3.ev.e[j];
813+
post_addr++;
814+
}
815+
}
816+
817+
if ((G_CUR_UAV & MASK_ALNK2) > 0)
818+
{
819+
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
820+
*L_DBG_UNIT = 1;
821+
post_addr = (uint64_t*) (POST_OFFSET_G2_A2 | PBA_ENABLE);
822+
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
823+
getscom_abs(G_PMULETS_2_2c[0], &u3.pmulet);
824+
for(j=0; j<4; j++)
825+
{
826+
*post_addr = (uint64_t)u3.ev.e[j];
827+
post_addr++;
828+
}
829+
getscom_abs(G_PMULETS_2_2c[1], &u3.pmulet);
830+
for(j=0; j<4; j++)
831+
{
832+
*post_addr = (uint64_t)u3.ev.e[j];
833+
post_addr++;
834+
}
835+
}
836+
if ((G_CUR_UAV & MASK_ALNK3) > 0)
837+
{
838+
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
839+
*L_DBG_UNIT = 1;
840+
post_addr = (uint64_t*) (POST_OFFSET_G2_A3 | PBA_ENABLE);
841+
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
842+
getscom_abs(G_PMULETS_2_2d[0], &u3.pmulet);
843+
for(j=0; j<4; j++)
844+
{
845+
*post_addr = (uint64_t)u3.ev.e[j];
846+
post_addr++;
847+
}
848+
getscom_abs(G_PMULETS_2_2d[1], &u3.pmulet);
849+
for(j=0; j<4; j++)
850+
{
851+
*post_addr = (uint64_t)u3.ev.e[j];
852+
post_addr++;
853+
}
854+
}
855+
}
745856
break;
746857
case G3://NVLINKS -NTL,ATS,XTS
747858
*L_DBG_GRP = 3;

‎src/occ_gpe1/gpe1_24x7.h

Lines changed: 44 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -28,11 +28,11 @@
2828

2929
//PMU config table defined below.
3030
//------------------------------
31-
#define TOTAL_CONFIGS 60
31+
#define TOTAL_CONFIGS 61
3232
#define TOTAL_POSTINGS 238
3333
#define INC_UPD_COUNT 1
3434

35-
#define TOTAL_CONFIG_SCOMS 60
35+
#define TOTAL_CONFIG_SCOMS 61
3636
#define TOTAL_COUNTER_SCOMS 71
3737

3838
#define MAX_32 4294967295ULL
@@ -77,7 +77,7 @@ uint64_t G_PMU_CONFIGS_8[][2] =
7777
{0x50108be, 0x00005345755b6000},//port2,3//26
7878
{0x50108bf, 0x000e800000000000},//port2,3//27
7979
//xlinks//
80-
{0x501341a, 0xff015daa15555000},//all xlinks//28
80+
{0x501341a, 0xff115daa15555000},//all xlinks//28
8181
//nx//
8282
{0x20110a6, 0xcaa0000080000000},//29
8383
{0x20110a9, 0xcaa0492480000000},//30
@@ -113,7 +113,9 @@ uint64_t G_PMU_CONFIGS_8[][2] =
113113
{0x4010816, 0x6000000000000000},//CAPP02//56
114114
{0x4010824, 0x8058914202000000},//CAPP02//57
115115
{0x4010822, 0x1000000000000000},//CAPP02//58
116-
{0x4010817, 0x0000000000000000} //CAPP02//59
116+
{0x4010817, 0x0000000000000000},//CAPP02//59
117+
//alinks//
118+
{0x501381a, 0xff115daa05555000}//all alinks//60
117119
};
118120

119121
uint64_t G_PMU_CONFIGS_16[][2] =
@@ -150,7 +152,7 @@ uint64_t G_PMU_CONFIGS_16[][2] =
150152
{0x50108be, 0x00005345755b6000},//port2,3//26
151153
{0x50108bf, 0x000e800000000000},//port2,3//27
152154
//xlinks
153-
{0x501341a, 0xff015d5515555000},//all xlinks//28
155+
{0x501341a, 0xff115d5515555000},//all xlinks//28
154156
//nx
155157
{0x20110a6, 0xc550000080000000},//29
156158
{0x20110a9, 0xc550492480000000},//30
@@ -186,7 +188,9 @@ uint64_t G_PMU_CONFIGS_16[][2] =
186188
{0x4010816, 0x6000000000000000},//CAPP02//56
187189
{0x4010824, 0x803850c102000000},//CAPP02//57
188190
{0x4010822, 0x1000000000000000},//CAPP02//58
189-
{0x4010817, 0x0000000000000000} //CAPP02//59
191+
{0x4010817, 0x0000000000000000},//CAPP02//59
192+
//alinks//
193+
{0x501341a, 0xff115d5505555000}//all alinks//60
190194
};
191195

192196

@@ -337,6 +341,31 @@ uint64_t G_PMULETS_7[] =
337341
0x4010825//6//70
338342
};
339343

344+
//Alink - fips920
345+
uint64_t G_PMULETS_2_2a[] =
346+
{//Alink0
347+
0x501381b,//0-even
348+
0x501381c,//1-odd
349+
};
350+
351+
uint64_t G_PMULETS_2_2b[] =
352+
{//Alink1
353+
0x501381d,//2-even
354+
0x501381e,//3-odd
355+
};
356+
357+
uint64_t G_PMULETS_2_2c[] =
358+
{//Alink2
359+
0x501381f,//4-even
360+
0x5013820,//5-odd
361+
};
362+
363+
uint64_t G_PMULETS_2_2d[] =
364+
{//Alink3
365+
0x5013821,//6-even
366+
0x5013822,//7-odd
367+
};
368+
340369
/**
341370
* Groups
342371
**/
@@ -375,7 +404,7 @@ enum
375404
POST_OFFSET_G2_4 = 0x001801D8,
376405
POST_OFFSET_G2T = 0x00180218,
377406

378-
// Group G3 - INTL
407+
// Group G3 - NTL
379408
POST_OFFSET_G3H = 0x00180220,
380409
POST_OFFSET_G3_1 = 0x00180228,
381410
POST_OFFSET_G3_2 = 0x00180248,
@@ -404,6 +433,10 @@ enum
404433
POST_OFFSET_G5_4 = 0x00180490,
405434
POST_OFFSET_G5T = 0x00180548,
406435

436+
// Group G2 - ALINK 0-1 - part of G5 MBA0-3
437+
POST_OFFSET_G2_A0 = 0x001804A8,
438+
POST_OFFSET_G2_A1 = 0x001804E8,
439+
407440
// Group G6 - MBA 4-7
408441
POST_OFFSET_G6H = 0x00180550,
409442
POST_OFFSET_G6_1 = 0x00180558,
@@ -412,6 +445,10 @@ enum
412445
POST_OFFSET_G6_4 = 0x001805A0,
413446
POST_OFFSET_G6T = 0x00180658,
414447

448+
// Group G2 - ALINK 2-3 - part of G5 MBA4-7
449+
POST_OFFSET_G2_A2 = 0x001805B8,
450+
POST_OFFSET_G2_A3 = 0x001805F8,
451+
415452
// Group G7 - NPCQ/CAPP
416453
POST_OFFSET_G7H = 0x00180660,
417454
POST_OFFSET_G7_1 = 0x00180668,

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