Toolchain flags errors for xpulp SIMD ALU instuctions cv.avgu.sci.{.h/.b} with 6-bit unsigned decimal notation for Imm6 operand

[dd-vaibhavjain]

Toolchain release:

corev-openhw-gcc-centos7-20230623

Issue Description:

XPULP SIMD ALU Instruction:

avgu.sci.h/b

SIMD ALU operations
cv32e40p-user-manual-en-cv32e40p_v1.3.2.pdf , Table 7.31 SIMD ALU operations

User Manual description:

cv.avgu[.sc,.sci]{.h,.b} rD, rs1, [rs2, Imm6] rD[i] = ((rs1[i] + op2[i]) & {0xFFFF, 0xFF}) >> 1
Note: Immediate is zero-extended, shift is logical.

This issue relates to a recent issue from the cv32e40p core's github repo Issue:
[https://github.com/openhwgroup/cv32e40p/issues/814]

After this referenced issue's (#814) fix, the User Manual is now updated to clarify the cv.avgu.sci Imm6 field to be zero-extended, i.e., unsigned 6-bit Immediate. And the User Manual v1.3.2 now explicitly specifies the Imm6 field to be "Zero-extended" for cv.avgu.sci.h/b instructions.
But at this release version of the toolchain, this User Manual update is not yet reflected in the toolchain, and as a result if the Imm6 field notation used in assembly code is for unsigned 6-bit decimal beyond decimal 31, the toolchain flags this as out-of-range error.

Error Example:

cv.avgu.sci.b a0, t5, 43
Error: immediate value must be 6-bit signed, 43 is out of range

Maybe the team is already aware of this related User Manual update but just raising this issue here to track and notify.

[NandniJamnadas]

Hi @dd-vaibhavjain, thanks for raising this issue. I have fixed this issue in here:

• CORE-V Binutils fix #97 CORE-V: SIMD Update: cv.or.sci[.h,.b], cv.xor.sci[.h,.b], cv.and.sci[.h,.b], cv.avgu.sci[.h,.b].
• CORE-V GCC fix #52 CORE-V: SIMD Update: cv.avgu.sc{i}[.h,.b] builtins from signed to unsigned.

[dd-vaibhavjain]

This issue was fixed and no longer seen in our tests. Closing this. Thanks @NandniJamnadas !