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Feature/flush ctrl in csrwrite #99

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christian-herber-nxp
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ctopal and others added 2 commits March 2, 2023 14:48
As Greg pointed out:

When we have an instruction in ID/EX that writes a PMP register that
update gets written to the CSR the same cycle the next instruction
moves from IF to ID/EX with it's PMP check done with the old value.

The solution is to flush the pipeline when we get a PMP CSR write.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
Without this an instruction executed immediately after the MSECCFG write
doesn't have the new MSECCFG setup applied to its execute permission.
@davideschiavone davideschiavone merged commit 91eb856 into openhwgroup:main Mar 3, 2023
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4 participants