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Feature/flush ctrl in csrwrite #99

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merged 2 commits into from
Mar 3, 2023
Merged

Feature/flush ctrl in csrwrite #99

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602b197
[rtl] Flush controller in PMP CSR write ops
ctopal Aug 3, 2022
e7373d7
[rtl] Flush pipe on MSECCFG CSR write
GregAC Nov 16, 2022
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11 changes: 8 additions & 3 deletions rtl/cve2_id_stage.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -438,7 +438,7 @@ module cve2_id_stage #(
);

/////////////////////////////////
// CSR-related pipline flushes //
// CSR-related pipeline flushes //
/////////////////////////////////
always_comb begin : csr_pipeline_flushes
csr_pipe_flush = 1'b0;
Expand All @@ -447,10 +447,15 @@ module cve2_id_stage #(
// - When enabling interrupts, pending IRQs become visible to the controller only during
// the next cycle. If during that cycle the core disables interrupts again, it does not
// see any pending IRQs and consequently does not start to handle interrupts.
// - When modifying any PMP CSR, PMP check of the next instruction might get invalidated.
// Hence, a pipeline flush is needed to instantiate another PMP check with the updated CSRs.
// - When modifying debug CSRs - TODO: Check if this is really needed
if (csr_op_en_o == 1'b1 && (csr_op_o == CSR_OP_WRITE || csr_op_o == CSR_OP_SET)) begin
if (csr_num_e'(instr_rdata_i[31:20]) == CSR_MSTATUS ||
csr_num_e'(instr_rdata_i[31:20]) == CSR_MIE) begin
if (csr_num_e'(instr_rdata_i[31:20]) == CSR_MSTATUS ||
csr_num_e'(instr_rdata_i[31:20]) == CSR_MIE ||
csr_num_e'(instr_rdata_i[31:20]) == CSR_MSECCFG ||
// To catch all PMPCFG/PMPADDR registers, get the shared top most 7 bits.
instr_rdata_i[31:25] == 7'h1D) begin
csr_pipe_flush = 1'b1;
end
end else if (csr_op_en_o == 1'b1 && csr_op_o != CSR_OP_READ) begin
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