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‎.github/workflows/submit.yml

Lines changed: 293 additions & 17 deletions
Large diffs are not rendered by default.

‎make/autoconf/spec.gmk.in

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -759,7 +759,6 @@ TAR_SUPPORTS_TRANSFORM:=@TAR_SUPPORTS_TRANSFORM@
759759

760760
# Build setup
761761
ENABLE_AOT:=@ENABLE_AOT@
762-
ENABLE_INTREE_EC:=@ENABLE_INTREE_EC@
763762
USE_EXTERNAL_LIBJPEG:=@USE_EXTERNAL_LIBJPEG@
764763
USE_EXTERNAL_LIBGIF:=@USE_EXTERNAL_LIBGIF@
765764
USE_EXTERNAL_LIBZ:=@USE_EXTERNAL_LIBZ@

‎make/data/tzdata/VERSION

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,4 +21,4 @@
2121
# or visit www.oracle.com if you need additional information or have any
2222
# questions.
2323
#
24-
tzdata2020b
24+
tzdata2020c

‎make/data/tzdata/australasia

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -404,6 +404,19 @@ Zone Indian/Cocos 6:27:40 - LMT 1900
404404
# From Michael Deckers (2019-08-06):
405405
# https://www.laws.gov.fj/LawsAsMade/downloadfile/848
406406

407+
# From Raymond Kumar (2020-10-08):
408+
# [DST in Fiji] is from December 20th 2020, till 17th January 2021.
409+
# From Alan Mintz (2020-10-08):
410+
# https://www.laws.gov.fj/LawsAsMade/GetFile/1071
411+
# From Tim Parenti (2020-10-08):
412+
# https://www.fijivillage.com/news/Daylight-saving-from-Dec-20th-this-year-to-Jan-17th-2021-8rf4x5/
413+
# "Minister for Employment, Parveen Bala says they had never thought of
414+
# stopping daylight saving. He says it was just to decide on when it should
415+
# start and end. Bala says it is a short period..."
416+
# Since the end date is still in line with our ongoing predictions, assume for
417+
# now that the later-than-usual start date is a one-time departure from the
418+
# recent second Sunday in November pattern.
419+
407420
# Rule NAME FROM TO - IN ON AT SAVE LETTER/S
408421
Rule Fiji 1998 1999 - Nov Sun>=1 2:00 1:00 -
409422
Rule Fiji 1999 2000 - Feb lastSun 3:00 0 -
@@ -415,7 +428,9 @@ Rule Fiji 2012 2013 - Jan Sun>=18 3:00 0 -
415428
Rule Fiji 2014 only - Jan Sun>=18 2:00 0 -
416429
Rule Fiji 2014 2018 - Nov Sun>=1 2:00 1:00 -
417430
Rule Fiji 2015 max - Jan Sun>=12 3:00 0 -
418-
Rule Fiji 2019 max - Nov Sun>=8 2:00 1:00 -
431+
Rule Fiji 2019 only - Nov Sun>=8 2:00 1:00 -
432+
Rule Fiji 2020 only - Dec 20 2:00 1:00 -
433+
Rule Fiji 2021 max - Nov Sun>=8 2:00 1:00 -
419434
# Zone NAME STDOFF RULES FORMAT [UNTIL]
420435
Zone Pacific/Fiji 11:55:44 - LMT 1915 Oct 26 # Suva
421436
12:00 Fiji +12/+13

‎make/data/tzdata/europe

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1612,6 +1612,8 @@ Rule Hungary 1946 only - Oct 7 2:00 0 -
16121612
# https://library.hungaricana.hu/hu/view/Zala_1948_09/?pg=64
16131613
# https://library.hungaricana.hu/hu/view/SatoraljaujhelyiLeveltar_ZempleniNepujsag_1948/?pg=53
16141614
# https://library.hungaricana.hu/hu/view/SatoraljaujhelyiLeveltar_ZempleniNepujsag_1948/?pg=160
1615+
# https://library.hungaricana.hu/hu/view/UjSzo_1949_01-04/?pg=102
1616+
# https://library.hungaricana.hu/hu/view/KeletMagyarorszag_1949_03/?pg=96
16151617
# https://library.hungaricana.hu/hu/view/Delmagyarorszag_1949_09/?pg=94
16161618
Rule Hungary 1947 1949 - Apr Sun>=4 2:00s 1:00 S
16171619
Rule Hungary 1947 1949 - Oct Sun>=1 2:00s 0 -
@@ -1627,9 +1629,10 @@ Rule Hungary 1955 only - Oct 2 3:00 0 -
16271629
# https://library.hungaricana.hu/hu/view/PestMegyeiHirlap_1957_09/?pg=143
16281630
Rule Hungary 1956 1957 - Jun Sun>=1 2:00 1:00 S
16291631
Rule Hungary 1956 1957 - Sep lastSun 3:00 0 -
1630-
# https://library.hungaricana.hu/hu/view/DTT_KOZL_TanacsokKozlonye_1980/?pg=1227
1632+
# https://library.hungaricana.hu/hu/view/DTT_KOZL_TanacsokKozlonye_1980/?pg=189
16311633
Rule Hungary 1980 only - Apr 6 0:00 1:00 S
16321634
Rule Hungary 1980 only - Sep 28 1:00 0 -
1635+
# https://library.hungaricana.hu/hu/view/DTT_KOZL_TanacsokKozlonye_1980/?pg=1227
16331636
# https://library.hungaricana.hu/hu/view/Delmagyarorszag_1981_01/?pg=79
16341637
# https://library.hungaricana.hu/hu/view/DTT_KOZL_TanacsokKozlonye_1982/?pg=115
16351638
# https://library.hungaricana.hu/hu/view/DTT_KOZL_TanacsokKozlonye_1983/?pg=85
@@ -1640,6 +1643,7 @@ Rule Hungary 1981 1983 - Sep lastSun 1:00 0 -
16401643
Zone Europe/Budapest 1:16:20 - LMT 1890 Nov 1
16411644
1:00 C-Eur CE%sT 1918
16421645
# https://library.hungaricana.hu/hu/view/OGYK_RT_1941/?pg=1204
1646+
# https://library.hungaricana.hu/hu/view/OGYK_RT_1942/?pg=3955
16431647
1:00 Hungary CE%sT 1941 Apr 7 23:00
16441648
1:00 C-Eur CE%sT 1945
16451649
1:00 Hungary CE%sT 1984

‎make/modules/java.base/Copy.gmk

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -182,12 +182,16 @@ endif
182182

183183
################################################################################
184184

185-
$(eval $(call SetupCopyFiles, COPY_NET_PROPERTIES, \
186-
FILES := $(TOPDIR)/src/java.base/share/conf/net.properties, \
187-
DEST := $(CONF_DST_DIR), \
188-
))
185+
NET_PROPERTIES_SRCS := $(TOPDIR)/src/java.base/share/conf/net.properties \
186+
$(TOPDIR)/src/java.base/$(OPENJDK_TARGET_OS_TYPE)/conf/net.properties
187+
188+
NET_PROPERTIES_DST := $(CONF_DST_DIR)/net.properties
189+
190+
$(NET_PROPERTIES_DST): $(NET_PROPERTIES_SRCS)
191+
$(call MakeTargetDir)
192+
$(CAT) $(NET_PROPERTIES_SRCS) > $@
189193

190-
TARGETS += $(COPY_NET_PROPERTIES)
194+
TARGETS += $(NET_PROPERTIES_DST)
191195

192196
ifeq ($(call isTargetOs, linux), true)
193197
$(eval $(call SetupCopyFiles, COPY_SDP_CONF, \

‎make/modules/jdk.crypto.ec/Lib.gmk

Lines changed: 0 additions & 49 deletions
This file was deleted.

‎make/test/BuildMicrobenchmark.gmk

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -90,11 +90,10 @@ $(eval $(call SetupJavaCompilation, BUILD_JDK_MICROBENCHMARK, \
9090
TARGET_RELEASE := $(TARGET_RELEASE_NEWJDK_UPGRADED), \
9191
SMALL_JAVA := false, \
9292
CLASSPATH := $(MICROBENCHMARK_CLASSPATH), \
93-
DISABLED_WARNINGS := processing rawtypes cast serial preview, \
93+
DISABLED_WARNINGS := processing rawtypes cast serial, \
9494
SRC := $(MICROBENCHMARK_SRC), \
9595
BIN := $(MICROBENCHMARK_CLASSES), \
9696
JAVA_FLAGS := --add-modules jdk.unsupported --limit-modules java.management, \
97-
JAVAC_FLAGS := --enable-preview, \
9897
))
9998

10099
$(BUILD_JDK_MICROBENCHMARK): $(JMH_COMPILE_JARS)

‎src/hotspot/cpu/aarch64/aarch64_sve.ad

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1329,7 +1329,7 @@ instruct vlsrL(vReg dst, vReg shift) %{
13291329

13301330
instruct vasrB_imm(vReg dst, vReg src, immI shift) %{
13311331
predicate(UseSVE > 0 && n->as_Vector()->length() >= 16);
1332-
match(Set dst (RShiftVB src shift));
1332+
match(Set dst (RShiftVB src (RShiftCntV shift)));
13331333
ins_cost(SVE_COST);
13341334
format %{ "sve_asr $dst, $src, $shift\t# vector (sve) (B)" %}
13351335
ins_encode %{
@@ -1348,7 +1348,7 @@ instruct vasrB_imm(vReg dst, vReg src, immI shift) %{
13481348

13491349
instruct vasrS_imm(vReg dst, vReg src, immI shift) %{
13501350
predicate(UseSVE > 0 && n->as_Vector()->length() >= 8);
1351-
match(Set dst (RShiftVS src shift));
1351+
match(Set dst (RShiftVS src (RShiftCntV shift)));
13521352
ins_cost(SVE_COST);
13531353
format %{ "sve_asr $dst, $src, $shift\t# vector (sve) (H)" %}
13541354
ins_encode %{
@@ -1367,7 +1367,7 @@ instruct vasrS_imm(vReg dst, vReg src, immI shift) %{
13671367

13681368
instruct vasrI_imm(vReg dst, vReg src, immI shift) %{
13691369
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4);
1370-
match(Set dst (RShiftVI src shift));
1370+
match(Set dst (RShiftVI src (RShiftCntV shift)));
13711371
ins_cost(SVE_COST);
13721372
format %{ "sve_asr $dst, $src, $shift\t# vector (sve) (S)" %}
13731373
ins_encode %{
@@ -1385,7 +1385,7 @@ instruct vasrI_imm(vReg dst, vReg src, immI shift) %{
13851385

13861386
instruct vasrL_imm(vReg dst, vReg src, immI shift) %{
13871387
predicate(UseSVE > 0 && n->as_Vector()->length() >= 2);
1388-
match(Set dst (RShiftVL src shift));
1388+
match(Set dst (RShiftVL src (RShiftCntV shift)));
13891389
ins_cost(SVE_COST);
13901390
format %{ "sve_asr $dst, $src, $shift\t# vector (sve) (D)" %}
13911391
ins_encode %{
@@ -1403,7 +1403,7 @@ instruct vasrL_imm(vReg dst, vReg src, immI shift) %{
14031403

14041404
instruct vlsrB_imm(vReg dst, vReg src, immI shift) %{
14051405
predicate(UseSVE > 0 && n->as_Vector()->length() >= 16);
1406-
match(Set dst (URShiftVB src shift));
1406+
match(Set dst (URShiftVB src (RShiftCntV shift)));
14071407
ins_cost(SVE_COST);
14081408
format %{ "sve_lsr $dst, $src, $shift\t# vector (sve) (B)" %}
14091409
ins_encode %{
@@ -1426,7 +1426,7 @@ instruct vlsrB_imm(vReg dst, vReg src, immI shift) %{
14261426

14271427
instruct vlsrS_imm(vReg dst, vReg src, immI shift) %{
14281428
predicate(UseSVE > 0 && n->as_Vector()->length() >= 8);
1429-
match(Set dst (URShiftVS src shift));
1429+
match(Set dst (URShiftVS src (RShiftCntV shift)));
14301430
ins_cost(SVE_COST);
14311431
format %{ "sve_lsr $dst, $src, $shift\t# vector (sve) (H)" %}
14321432
ins_encode %{
@@ -1436,7 +1436,7 @@ instruct vlsrS_imm(vReg dst, vReg src, immI shift) %{
14361436
as_FloatRegister($src$$reg));
14371437
return;
14381438
}
1439-
if (con >= 8) {
1439+
if (con >= 16) {
14401440
__ sve_eor(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
14411441
as_FloatRegister($src$$reg));
14421442
return;
@@ -1449,7 +1449,7 @@ instruct vlsrS_imm(vReg dst, vReg src, immI shift) %{
14491449

14501450
instruct vlsrI_imm(vReg dst, vReg src, immI shift) %{
14511451
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4);
1452-
match(Set dst (URShiftVI src shift));
1452+
match(Set dst (URShiftVI src (RShiftCntV shift)));
14531453
ins_cost(SVE_COST);
14541454
format %{ "sve_lsr $dst, $src, $shift\t# vector (sve) (S)" %}
14551455
ins_encode %{
@@ -1467,7 +1467,7 @@ instruct vlsrI_imm(vReg dst, vReg src, immI shift) %{
14671467

14681468
instruct vlsrL_imm(vReg dst, vReg src, immI shift) %{
14691469
predicate(UseSVE > 0 && n->as_Vector()->length() >= 2);
1470-
match(Set dst (URShiftVL src shift));
1470+
match(Set dst (URShiftVL src (RShiftCntV shift)));
14711471
ins_cost(SVE_COST);
14721472
format %{ "sve_lsr $dst, $src, $shift\t# vector (sve) (D)" %}
14731473
ins_encode %{
@@ -1485,7 +1485,7 @@ instruct vlsrL_imm(vReg dst, vReg src, immI shift) %{
14851485

14861486
instruct vlslB_imm(vReg dst, vReg src, immI shift) %{
14871487
predicate(UseSVE > 0 && n->as_Vector()->length() >= 16);
1488-
match(Set dst (LShiftVB src shift));
1488+
match(Set dst (LShiftVB src (LShiftCntV shift)));
14891489
ins_cost(SVE_COST);
14901490
format %{ "sve_lsl $dst, $src, $shift\t# vector (sve) (B)" %}
14911491
ins_encode %{
@@ -1503,12 +1503,12 @@ instruct vlslB_imm(vReg dst, vReg src, immI shift) %{
15031503

15041504
instruct vlslS_imm(vReg dst, vReg src, immI shift) %{
15051505
predicate(UseSVE > 0 && n->as_Vector()->length() >= 8);
1506-
match(Set dst (LShiftVS src shift));
1506+
match(Set dst (LShiftVS src (LShiftCntV shift)));
15071507
ins_cost(SVE_COST);
15081508
format %{ "sve_lsl $dst, $src, $shift\t# vector (sve) (H)" %}
15091509
ins_encode %{
15101510
int con = (int)$shift$$constant;
1511-
if (con >= 8) {
1511+
if (con >= 16) {
15121512
__ sve_eor(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
15131513
as_FloatRegister($src$$reg));
15141514
return;
@@ -1521,7 +1521,7 @@ instruct vlslS_imm(vReg dst, vReg src, immI shift) %{
15211521

15221522
instruct vlslI_imm(vReg dst, vReg src, immI shift) %{
15231523
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4);
1524-
match(Set dst (LShiftVI src shift));
1524+
match(Set dst (LShiftVI src (LShiftCntV shift)));
15251525
ins_cost(SVE_COST);
15261526
format %{ "sve_lsl $dst, $src, $shift\t# vector (sve) (S)" %}
15271527
ins_encode %{
@@ -1534,7 +1534,7 @@ instruct vlslI_imm(vReg dst, vReg src, immI shift) %{
15341534

15351535
instruct vlslL_imm(vReg dst, vReg src, immI shift) %{
15361536
predicate(UseSVE > 0 && n->as_Vector()->length() >= 2);
1537-
match(Set dst (LShiftVL src shift));
1537+
match(Set dst (LShiftVL src (LShiftCntV shift)));
15381538
ins_cost(SVE_COST);
15391539
format %{ "sve_lsl $dst, $src, $shift\t# vector (sve) (D)" %}
15401540
ins_encode %{

‎src/hotspot/cpu/aarch64/aarch64_sve_ad.m4

Lines changed: 27 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -727,14 +727,14 @@ instruct $1(vReg dst, vReg shift) %{
727727
ins_pipe(pipe_slow);
728728
%}')dnl
729729
dnl
730-
dnl VSHIFT_IMM_UNPREDICATE($1, $2, $3, $4, $5 )
731-
dnl VSHIFT_IMM_UNPREDICATE(insn_name, op_name, size, min_vec_len, insn)
730+
dnl VSHIFT_IMM_UNPREDICATE($1, $2, $3, $4, $5, $6 )
731+
dnl VSHIFT_IMM_UNPREDICATE(insn_name, op_name, op_name2, size, min_vec_len, insn)
732732
define(`VSHIFT_IMM_UNPREDICATE', `
733733
instruct $1(vReg dst, vReg src, immI shift) %{
734-
predicate(UseSVE > 0 && n->as_Vector()->length() >= $4);
735-
match(Set dst ($2 src shift));
734+
predicate(UseSVE > 0 && n->as_Vector()->length() >= $5);
735+
match(Set dst ($2 src ($3 shift)));
736736
ins_cost(SVE_COST);
737-
format %{ "$5 $dst, $src, $shift\t# vector (sve) ($3)" %}
737+
format %{ "$6 $dst, $src, $shift\t# vector (sve) ($4)" %}
738738
ins_encode %{
739739
int con = (int)$shift$$constant;dnl
740740
ifelse(eval(index(`$1', `vasr') == 0 || index(`$1', `vlsr') == 0), 1, `
@@ -743,16 +743,21 @@ ifelse(eval(index(`$1', `vasr') == 0 || index(`$1', `vlsr') == 0), 1, `
743743
as_FloatRegister($src$$reg));
744744
return;
745745
}')dnl
746-
ifelse(eval(index(`$1', `vasr') == 0), 1, `ifelse(eval(index(`$3', `B') == 0), 1, `
747-
if (con >= 8) con = 7;')ifelse(eval(index(`$3', `H') == 0), 1, `
746+
ifelse(eval(index(`$1', `vasr') == 0), 1, `ifelse(eval(index(`$4', `B') == 0), 1, `
747+
if (con >= 8) con = 7;')ifelse(eval(index(`$4', `H') == 0), 1, `
748748
if (con >= 16) con = 15;')')dnl
749-
ifelse(eval((index(`$1', `vlsl') == 0 || index(`$1', `vlsr') == 0) && (index(`$3', `B') == 0 || index(`$3', `H') == 0)), 1, `
749+
ifelse(eval(index(`$1', `vlsl') == 0 || index(`$1', `vlsr') == 0), 1, `ifelse(eval(index(`$4', `B') == 0), 1, `
750750
if (con >= 8) {
751751
__ sve_eor(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
752752
as_FloatRegister($src$$reg));
753753
return;
754-
}')
755-
__ $5(as_FloatRegister($dst$$reg), __ $3,
754+
}')ifelse(eval(index(`$4', `H') == 0), 1, `
755+
if (con >= 16) {
756+
__ sve_eor(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
757+
as_FloatRegister($src$$reg));
758+
return;
759+
}')')
760+
__ $6(as_FloatRegister($dst$$reg), __ $4,
756761
as_FloatRegister($src$$reg), con);
757762
%}
758763
ins_pipe(pipe_slow);
@@ -786,18 +791,18 @@ VSHIFT_TRUE_PREDICATE(vlsrB, URShiftVB, B, 16, sve_lsr)
786791
VSHIFT_TRUE_PREDICATE(vlsrS, URShiftVS, H, 8, sve_lsr)
787792
VSHIFT_TRUE_PREDICATE(vlsrI, URShiftVI, S, 4, sve_lsr)
788793
VSHIFT_TRUE_PREDICATE(vlsrL, URShiftVL, D, 2, sve_lsr)
789-
VSHIFT_IMM_UNPREDICATE(vasrB_imm, RShiftVB, B, 16, sve_asr)
790-
VSHIFT_IMM_UNPREDICATE(vasrS_imm, RShiftVS, H, 8, sve_asr)
791-
VSHIFT_IMM_UNPREDICATE(vasrI_imm, RShiftVI, S, 4, sve_asr)
792-
VSHIFT_IMM_UNPREDICATE(vasrL_imm, RShiftVL, D, 2, sve_asr)
793-
VSHIFT_IMM_UNPREDICATE(vlsrB_imm, URShiftVB, B, 16, sve_lsr)
794-
VSHIFT_IMM_UNPREDICATE(vlsrS_imm, URShiftVS, H, 8, sve_lsr)
795-
VSHIFT_IMM_UNPREDICATE(vlsrI_imm, URShiftVI, S, 4, sve_lsr)
796-
VSHIFT_IMM_UNPREDICATE(vlsrL_imm, URShiftVL, D, 2, sve_lsr)
797-
VSHIFT_IMM_UNPREDICATE(vlslB_imm, LShiftVB, B, 16, sve_lsl)
798-
VSHIFT_IMM_UNPREDICATE(vlslS_imm, LShiftVS, H, 8, sve_lsl)
799-
VSHIFT_IMM_UNPREDICATE(vlslI_imm, LShiftVI, S, 4, sve_lsl)
800-
VSHIFT_IMM_UNPREDICATE(vlslL_imm, LShiftVL, D, 2, sve_lsl)
794+
VSHIFT_IMM_UNPREDICATE(vasrB_imm, RShiftVB, RShiftCntV, B, 16, sve_asr)
795+
VSHIFT_IMM_UNPREDICATE(vasrS_imm, RShiftVS, RShiftCntV, H, 8, sve_asr)
796+
VSHIFT_IMM_UNPREDICATE(vasrI_imm, RShiftVI, RShiftCntV, S, 4, sve_asr)
797+
VSHIFT_IMM_UNPREDICATE(vasrL_imm, RShiftVL, RShiftCntV, D, 2, sve_asr)
798+
VSHIFT_IMM_UNPREDICATE(vlsrB_imm, URShiftVB, RShiftCntV, B, 16, sve_lsr)
799+
VSHIFT_IMM_UNPREDICATE(vlsrS_imm, URShiftVS, RShiftCntV, H, 8, sve_lsr)
800+
VSHIFT_IMM_UNPREDICATE(vlsrI_imm, URShiftVI, RShiftCntV, S, 4, sve_lsr)
801+
VSHIFT_IMM_UNPREDICATE(vlsrL_imm, URShiftVL, RShiftCntV, D, 2, sve_lsr)
802+
VSHIFT_IMM_UNPREDICATE(vlslB_imm, LShiftVB, LShiftCntV, B, 16, sve_lsl)
803+
VSHIFT_IMM_UNPREDICATE(vlslS_imm, LShiftVS, LShiftCntV, H, 8, sve_lsl)
804+
VSHIFT_IMM_UNPREDICATE(vlslI_imm, LShiftVI, LShiftCntV, S, 4, sve_lsl)
805+
VSHIFT_IMM_UNPREDICATE(vlslL_imm, LShiftVL, LShiftCntV, D, 2, sve_lsl)
801806
VSHIFT_COUNT(vshiftcntB, B, 16, T_BYTE)
802807
VSHIFT_COUNT(vshiftcntS, H, 8, T_SHORT)
803808
VSHIFT_COUNT(vshiftcntI, S, 4, T_INT)

‎src/hotspot/cpu/aarch64/globals_aarch64.hpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,8 @@ define_pd_global(intx, InlineSmallCode, 1000);
9393
"Use SIMD instructions in generated array equals code") \
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product(bool, UseSimpleArrayEquals, false, \
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"Use simpliest and shortest implementation for array equals") \
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product(bool, UseSIMDForBigIntegerShiftIntrinsics, true, \
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"Use SIMD instructions for left/right shift of BigInteger") \
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product(bool, AvoidUnalignedAccesses, false, \
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"Avoid generating unaligned memory accesses") \
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product(bool, UseLSE, false, \

‎src/hotspot/cpu/aarch64/interp_masm_aarch64.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -551,7 +551,9 @@ void InterpreterMacroAssembler::remove_activation(
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br(Assembler::AL, fast_path);
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bind(slow_path);
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push(state);
554-
call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::at_unwind));
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set_last_Java_frame(esp, rfp, (address)pc(), rscratch1);
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super_call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::at_unwind), rthread);
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reset_last_Java_frame(true);
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pop(state);
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bind(fast_path);
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