8254966: Remove unused code from Matcher

Reviewed-by: neliasso, kvn

Author: cl4es

src/hotspot/cpu/aarch64/aarch64.ad

@@ -614,9 +614,7 @@ alloc_class chunk3(RFLAGS);
 // Several register classes are automatically defined based upon information in
 // this architecture description.
 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )
-// 2) reg_class compiler_method_reg        ( /* as def'd in frame section */ )
-// 2) reg_class interpreter_method_reg     ( /* as def'd in frame section */ )
-// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
+// 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 //
 
 // Class for all 32 bit general purpose registers
@@ -2608,11 +2606,6 @@ const bool Matcher::rematerialize_float_constants = false;
 // C code as the Java calling convention forces doubles to be aligned.
 const bool Matcher::misaligned_doubles_ok = true;
 
-// No-op on amd64
-void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
-  Unimplemented();
-}
-
 // Advertise here if the CPU requires explicit rounding operations to implement strictfp mode.
 const bool Matcher::strict_fp_requires_explicit_rounding = false;
 
@@ -4090,9 +4083,6 @@ frame %{
   // Inline Cache Register or Method for I2C.
   inline_cache_reg(R12);
 
-  // Method Register when calling interpreter.
-  interpreter_method_reg(R12);
-
   // Number of stack slots consumed by locking an object
   sync_stack_slots(2);
 
@@ -5680,16 +5670,6 @@ operand inline_cache_RegP(iRegP reg)
   interface(REG_INTER);
 %}
 
-operand interpreter_method_RegP(iRegP reg)
-%{
-  constraint(ALLOC_IN_RC(method_reg)); // interpreter_method_reg
-  match(reg);
-  match(iRegPNoSp);
-  op_cost(0);
-  format %{ %}
-  interface(REG_INTER);
-%}
-
 // Thread Register
 operand thread_RegP(iRegP reg)
 %{

src/hotspot/cpu/arm/arm.ad

@@ -1159,10 +1159,6 @@ const bool Matcher::rematerialize_float_constants = false;
 // Java calling convention forces doubles to be aligned.
 const bool Matcher::misaligned_doubles_ok = false;
 
-// No-op on ARM.
-void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
-}
-
 // Advertise here if the CPU requires explicit rounding operations to implement strictfp mode.
 const bool Matcher::strict_fp_requires_explicit_rounding = false;
 
@@ -1667,7 +1663,6 @@ frame %{
   // These two registers define part of the calling convention
   // between compiled code and the interpreter.
   inline_cache_reg(R_Ricklass);          // Inline Cache Register or Method* for I2C
-  interpreter_method_reg(R_Rmethod);     // Method Register when calling interpreter
 
   // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
   cisc_spilling_operand_name(indOffset);
@@ -2527,14 +2522,6 @@ operand inline_cache_regP(iRegP reg) %{
   interface(REG_INTER);
 %}
 
-operand interpreter_method_regP(iRegP reg) %{
-  constraint(ALLOC_IN_RC(Rmethod_regP));
-  match(reg);
-  format %{ %}
-  interface(REG_INTER);
-%}
-
-
 //----------Complex Operands---------------------------------------------------
 // Indirect Memory Reference
 operand indirect(sp_ptr_RegP reg) %{

src/hotspot/cpu/arm/arm_32.ad

@@ -182,11 +182,11 @@ alloc_class chunk0(
 alloc_class chunk1(
                    R_S16, R_S17, R_S18, R_S19, R_S20, R_S21, R_S22, R_S23,
                    R_S24, R_S25, R_S26, R_S27, R_S28, R_S29, R_S30, R_S31,
-                   R_S0,  R_S1,  R_S2,  R_S3,  R_S4,  R_S5,  R_S6,  R_S7, 
+                   R_S0,  R_S1,  R_S2,  R_S3,  R_S4,  R_S5,  R_S6,  R_S7,
                    R_S8,  R_S9,  R_S10, R_S11, R_S12, R_S13, R_S14, R_S15,
-                   R_D16, R_D16x,R_D17, R_D17x,R_D18, R_D18x,R_D19, R_D19x, 
-                   R_D20, R_D20x,R_D21, R_D21x,R_D22, R_D22x,R_D23, R_D23x, 
-                   R_D24, R_D24x,R_D25, R_D25x,R_D26, R_D26x,R_D27, R_D27x, 
+                   R_D16, R_D16x,R_D17, R_D17x,R_D18, R_D18x,R_D19, R_D19x,
+                   R_D20, R_D20x,R_D21, R_D21x,R_D22, R_D22x,R_D23, R_D23x,
+                   R_D24, R_D24x,R_D25, R_D25x,R_D26, R_D26x,R_D27, R_D27x,
                    R_D28, R_D28x,R_D29, R_D29x,R_D30, R_D30x,R_D31, R_D31x
 );
 
@@ -196,8 +196,7 @@ alloc_class chunk2(APSR, FPSCR);
 // Several register classes are automatically defined based upon information in
 // this architecture description.
 // 1) reg_class inline_cache_reg           ( as defined in frame section )
-// 2) reg_class interpreter_method_reg     ( as defined in frame section )
-// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
+// 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 //
 
 // ----------------------------
@@ -223,7 +222,6 @@ reg_class ptr_reg(R_R0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_
 reg_class sp_ptr_reg(R_R0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R11, R_R12, R_R14, R_R10 /* TLS*/, R_R13 /* SP*/);
 
 #define R_Ricklass R_R8
-#define R_Rmethod  R_R9
 #define R_Rthread  R_R10
 #define R_Rexception_obj R_R4
 
@@ -237,7 +235,6 @@ reg_class R9_regP(R_R9);
 reg_class R12_regP(R_R12);
 reg_class Rexception_regP(R_Rexception_obj);
 reg_class Ricklass_regP(R_Ricklass);
-reg_class Rmethod_regP(R_Rmethod);
 reg_class Rthread_regP(R_Rthread);
 reg_class IP_regP(R_R12);
 reg_class SP_regP(R_R13);
@@ -442,7 +439,7 @@ int MachCallStaticJavaNode::ret_addr_offset() {
 int MachCallDynamicJavaNode::ret_addr_offset() {
   bool far = !cache_reachable();
   // mov_oop is always 2 words
-  return (2 + (far ? 3 : 1)) * NativeInstruction::instruction_size; 
+  return (2 + (far ? 3 : 1)) * NativeInstruction::instruction_size;
 }
 
 int MachCallRuntimeNode::ret_addr_offset() {

src/hotspot/cpu/ppc/ppc.ad

@@ -535,9 +535,7 @@ alloc_class chunk4 (
 // information in this architecture description.
 
 // 1) reg_class inline_cache_reg           ( as defined in frame section )
-// 2) reg_class compiler_method_reg        ( as defined in frame section )
-// 2) reg_class interpreter_method_reg     ( as defined in frame section )
-// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
+// 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 //
 
 // ----------------------------
@@ -2344,10 +2342,6 @@ const bool Matcher::rematerialize_float_constants = false;
 // Java calling convention forces doubles to be aligned.
 const bool Matcher::misaligned_doubles_ok = true;
 
-void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
- Unimplemented();
-}
-
 // Advertise here if the CPU requires explicit rounding operations to implement strictfp mode.
 const bool Matcher::strict_fp_requires_explicit_rounding = false;
 
@@ -3859,9 +3853,6 @@ frame %{
   // Inline Cache Register or method for I2C.
   inline_cache_reg(R19); // R19_method
 
-  // Method Register when calling interpreter.
-  interpreter_method_reg(R19); // R19_method
-
   // Optional: name the operand used by cisc-spilling to access
   // [stack_pointer + offset].
   cisc_spilling_operand_name(indOffset);
@@ -4769,20 +4760,6 @@ operand inline_cache_regP(iRegPdst reg) %{
   interface(REG_INTER);
 %}
 
-operand compiler_method_regP(iRegPdst reg) %{
-  constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_reg
-  match(reg);
-  format %{ %}
-  interface(REG_INTER);
-%}
-
-operand interpreter_method_regP(iRegPdst reg) %{
-  constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_reg
-  match(reg);
-  format %{ %}
-  interface(REG_INTER);
-%}
-
 // Operands to remove register moves in unscaled mode.
 // Match read/write registers with an EncodeP node if neither shift nor add are required.
 operand iRegP2N(iRegPsrc reg) %{

src/hotspot/cpu/s390/s390.ad

@@ -278,9 +278,7 @@ alloc_class chunk2(
 // information in this architecture description.
 
 // 1) reg_class inline_cache_reg           (as defined in frame section)
-// 2) reg_class compiler_method_reg        (as defined in frame section)
-// 2) reg_class interpreter_method_reg     (as defined in frame section)
-// 3) reg_class stack_slots(/* one chunk of stack-based "registers" */)
+// 2) reg_class stack_slots(/* one chunk of stack-based "registers" */)
 
 // Integer Register Classes
 reg_class z_int_reg(
@@ -2466,12 +2464,6 @@ frame %{
   // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6.
   // interpreter_arg_ptr_reg(Z_R6);
 
-  // Temporary in compiled entry-points
-  // compiler_method_reg(Z_R1);//Z_R1_scratch
-
-  // Method Register when calling interpreter
-  interpreter_method_reg(Z_R9);//Z_method
-
   // Optional: name the operand used by cisc-spilling to access
   // [stack_pointer + offset].
   cisc_spilling_operand_name(indOffset12);
@@ -3535,20 +3527,6 @@ operand inline_cache_regP(iRegP reg) %{
   interface(REG_INTER);
 %}
 
-operand compiler_method_regP(iRegP reg) %{
-  constraint(ALLOC_IN_RC(z_r1_RegP)); // compiler_method_reg
-  match(reg);
-  format %{ %}
-  interface(REG_INTER);
-%}
-
-operand interpreter_method_regP(iRegP reg) %{
-  constraint(ALLOC_IN_RC(z_r9_regP)); // interpreter_method_reg
-  match(reg);
-  format %{ %}
-  interface(REG_INTER);
-%}
-
 // Operands to remove register moves in unscaled mode.
 // Match read/write registers with an EncodeP node if neither shift nor add are required.
 operand iRegP2N(iRegP reg) %{