Skip to content

Commit ba174af

Browse files
author
Joshua Zhu
committed
8253048: AArch64: When CallLeaf, no need to preserve callee-saved registers in caller
Reviewed-by: adinn, aph
1 parent 3320fc0 commit ba174af

File tree

2 files changed

+22
-22
lines changed

2 files changed

+22
-22
lines changed

‎src/hotspot/cpu/aarch64/aarch64.ad

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -247,71 +247,71 @@ reg_def R31_H ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg()->next());
247247
reg_def V7_N ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(6) );
248248
reg_def V7_O ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(7) );
249249

250-
reg_def V8 ( SOC, SOC, Op_RegF, 8, v8->as_VMReg() );
251-
reg_def V8_H ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next() );
250+
reg_def V8 ( SOC, SOE, Op_RegF, 8, v8->as_VMReg() );
251+
reg_def V8_H ( SOC, SOE, Op_RegF, 8, v8->as_VMReg()->next() );
252252
reg_def V8_J ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(2) );
253253
reg_def V8_K ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(3) );
254254
reg_def V8_L ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(4) );
255255
reg_def V8_M ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(5) );
256256
reg_def V8_N ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(6) );
257257
reg_def V8_O ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(7) );
258258

259-
reg_def V9 ( SOC, SOC, Op_RegF, 9, v9->as_VMReg() );
260-
reg_def V9_H ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next() );
259+
reg_def V9 ( SOC, SOE, Op_RegF, 9, v9->as_VMReg() );
260+
reg_def V9_H ( SOC, SOE, Op_RegF, 9, v9->as_VMReg()->next() );
261261
reg_def V9_J ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(2) );
262262
reg_def V9_K ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(3) );
263263
reg_def V9_L ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(4) );
264264
reg_def V9_M ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(5) );
265265
reg_def V9_N ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(6) );
266266
reg_def V9_O ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(7) );
267267

268-
reg_def V10 ( SOC, SOC, Op_RegF, 10, v10->as_VMReg() );
269-
reg_def V10_H ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next() );
268+
reg_def V10 ( SOC, SOE, Op_RegF, 10, v10->as_VMReg() );
269+
reg_def V10_H ( SOC, SOE, Op_RegF, 10, v10->as_VMReg()->next() );
270270
reg_def V10_J ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(2) );
271271
reg_def V10_K ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(3) );
272272
reg_def V10_L ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(4) );
273273
reg_def V10_M ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(5) );
274274
reg_def V10_N ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(6) );
275275
reg_def V10_O ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(7) );
276276

277-
reg_def V11 ( SOC, SOC, Op_RegF, 11, v11->as_VMReg() );
278-
reg_def V11_H ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next() );
277+
reg_def V11 ( SOC, SOE, Op_RegF, 11, v11->as_VMReg() );
278+
reg_def V11_H ( SOC, SOE, Op_RegF, 11, v11->as_VMReg()->next() );
279279
reg_def V11_J ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(2) );
280280
reg_def V11_K ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(3) );
281281
reg_def V11_L ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(4) );
282282
reg_def V11_M ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(5) );
283283
reg_def V11_N ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(6) );
284284
reg_def V11_O ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(7) );
285285

286-
reg_def V12 ( SOC, SOC, Op_RegF, 12, v12->as_VMReg() );
287-
reg_def V12_H ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next() );
286+
reg_def V12 ( SOC, SOE, Op_RegF, 12, v12->as_VMReg() );
287+
reg_def V12_H ( SOC, SOE, Op_RegF, 12, v12->as_VMReg()->next() );
288288
reg_def V12_J ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(2) );
289289
reg_def V12_K ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(3) );
290290
reg_def V12_L ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(4) );
291291
reg_def V12_M ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(5) );
292292
reg_def V12_N ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(6) );
293293
reg_def V12_O ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(7) );
294294

295-
reg_def V13 ( SOC, SOC, Op_RegF, 13, v13->as_VMReg() );
296-
reg_def V13_H ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next() );
295+
reg_def V13 ( SOC, SOE, Op_RegF, 13, v13->as_VMReg() );
296+
reg_def V13_H ( SOC, SOE, Op_RegF, 13, v13->as_VMReg()->next() );
297297
reg_def V13_J ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(2) );
298298
reg_def V13_K ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(3) );
299299
reg_def V13_L ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(4) );
300300
reg_def V13_M ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(5) );
301301
reg_def V13_N ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(6) );
302302
reg_def V13_O ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(7) );
303303

304-
reg_def V14 ( SOC, SOC, Op_RegF, 14, v14->as_VMReg() );
305-
reg_def V14_H ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next() );
304+
reg_def V14 ( SOC, SOE, Op_RegF, 14, v14->as_VMReg() );
305+
reg_def V14_H ( SOC, SOE, Op_RegF, 14, v14->as_VMReg()->next() );
306306
reg_def V14_J ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(2) );
307307
reg_def V14_K ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(3) );
308308
reg_def V14_L ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(4) );
309309
reg_def V14_M ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(5) );
310310
reg_def V14_N ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(6) );
311311
reg_def V14_O ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(7) );
312312

313-
reg_def V15 ( SOC, SOC, Op_RegF, 15, v15->as_VMReg() );
314-
reg_def V15_H ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next() );
313+
reg_def V15 ( SOC, SOE, Op_RegF, 15, v15->as_VMReg() );
314+
reg_def V15_H ( SOC, SOE, Op_RegF, 15, v15->as_VMReg()->next() );
315315
reg_def V15_J ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(2) );
316316
reg_def V15_K ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(3) );
317317
reg_def V15_L ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(4) );

‎src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -360,7 +360,7 @@ void MacroAssembler::generate__ieee754_rem_pio2(address npio2_hw,
360360
lsr(rscratch1, ix, 20); // ix >> 20
361361
movz(tmp5, 0x4170, 48);
362362
subw(rscratch1, rscratch1, 1046); // e0
363-
fmovd(v10, tmp5); // init two24A value
363+
fmovd(v24, tmp5); // init two24A value
364364
subw(jv, ix, rscratch1, LSL, 20); // ix - (e0<<20)
365365
lsl(jv, jv, 32);
366366
subw(rscratch2, rscratch1, 3);
@@ -374,7 +374,7 @@ void MacroAssembler::generate__ieee754_rem_pio2(address npio2_hw,
374374
sdivw(jv, rscratch2, i); // jv = (e0 - 3)/24
375375
fsubd(v26, v26, v6);
376376
sub(sp, sp, 560);
377-
fmuld(v26, v26, v10);
377+
fmuld(v26, v26, v24);
378378
frintzd(v7, v26); // v7 = (double)((int)v26)
379379
movw(jx, 2); // calculate jx as nx - 1, which is initially 2. Not a part of unrolled loop
380380
fsubd(v26, v26, v7);
@@ -383,7 +383,7 @@ void MacroAssembler::generate__ieee754_rem_pio2(address npio2_hw,
383383
block_comment("nx calculation with unrolled while(tx[nx-1]==zeroA) nx--;"); {
384384
fcmpd(v26, 0.0); // if NE then jx == 2. else it's 1 or 0
385385
add(iqBase, sp, 480); // base of iq[]
386-
fmuld(v3, v26, v10);
386+
fmuld(v3, v26, v24);
387387
br(NE, NX_SET);
388388
fcmpd(v7, 0.0); // v7 == 0 => jx = 0. Else jx = 1
389389
csetw(jx, NE);
@@ -839,7 +839,7 @@ void MacroAssembler::generate__kernel_rem_pio2(address two_over_pi, address pio2
839839
ldrd(v27, post(tmp2, -8));
840840
fmuld(v29, v17, v18); // twon24*z
841841
frintzd(v29, v29); // (double)(int)
842-
fmsubd(v28, v10, v29, v18); // v28 = z-two24A*fw
842+
fmsubd(v28, v24, v29, v18); // v28 = z-two24A*fw
843843
fcvtzdw(tmp1, v28); // (int)(z-two24A*fw)
844844
strw(tmp1, Address(iqBase, i, Address::lsl(2)));
845845
faddd(v18, v27, v29);
@@ -1000,11 +1000,11 @@ void MacroAssembler::generate__kernel_rem_pio2(address two_over_pi, address pio2
10001000
block_comment("else block of if(z==0.0) {"); {
10011001
bind(RECOMP_CHECK_DONE_NOT_ZERO);
10021002
fmuld(v18, v18, v22);
1003-
fcmpd(v18, v10); // v10 is stil two24A
1003+
fcmpd(v18, v24); // v24 is stil two24A
10041004
br(LT, Z_IS_LESS_THAN_TWO24B);
10051005
fmuld(v1, v18, v17); // twon24*z
10061006
frintzd(v1, v1); // v1 = (double)(int)(v1)
1007-
fmsubd(v2, v10, v1, v18);
1007+
fmsubd(v2, v24, v1, v18);
10081008
fcvtzdw(tmp3, v1); // (int)fw
10091009
fcvtzdw(tmp2, v2); // double to int
10101010
strw(tmp2, Address(iqBase, jz, Address::lsl(2)));

0 commit comments

Comments
 (0)