8188764: Obsolete AssumeMP and then remove all support for non-MP builds

Reviewed-by: mikael, mdoerr, bulasevich, eosterlund

Author: David Holmes

src/hotspot/cpu/aarch64/compiledIC_aarch64.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, 2018, Red Hat Inc. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
@@ -195,9 +195,7 @@ void CompiledDirectStaticCall::set_stub_to_clean(static_stub_Relocation* static_
 void CompiledDirectStaticCall::verify() {
   // Verify call.
   _call->verify();
-  if (os::is_MP()) {
-    _call->verify_alignment();
-  }
+  _call->verify_alignment();
 
   // Verify stub.
   address stub = find_stub(false /* is_aot */);

src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp

@@ -1950,24 +1950,20 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
   //     didn't see any synchronization is progress, and escapes.
   __ mov(rscratch1, _thread_in_native_trans);
 
-  if(os::is_MP()) {
-    if (UseMembar) {
-      __ strw(rscratch1, Address(rthread, JavaThread::thread_state_offset()));
+  if (UseMembar) {
+    __ strw(rscratch1, Address(rthread, JavaThread::thread_state_offset()));
 
-      // Force this write out before the read below
-      __ dmb(Assembler::ISH);
-    } else {
-      __ lea(rscratch2, Address(rthread, JavaThread::thread_state_offset()));
-      __ stlrw(rscratch1, rscratch2);
-
-      // Write serialization page so VM thread can do a pseudo remote membar.
-      // We use the current thread pointer to calculate a thread specific
-      // offset to write to within the page. This minimizes bus traffic
-      // due to cache line collision.
-      __ serialize_memory(rthread, r2);
-    }
+    // Force this write out before the read below
+    __ dmb(Assembler::ISH);
   } else {
-    __ strw(rscratch1, Address(rthread, JavaThread::thread_state_offset()));
+    __ lea(rscratch2, Address(rthread, JavaThread::thread_state_offset()));
+    __ stlrw(rscratch1, rscratch2);
+
+    // Write serialization page so VM thread can do a pseudo remote membar.
+    // We use the current thread pointer to calculate a thread specific
+    // offset to write to within the page. This minimizes bus traffic
+    // due to cache line collision.
+    __ serialize_memory(rthread, r2);
   }
 
   // check for safepoint operation in progress and/or pending suspend requests

src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp

@@ -1394,17 +1394,15 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) {
   __ lea(rscratch2, Address(rthread, JavaThread::thread_state_offset()));
   __ stlrw(rscratch1, rscratch2);
 
-  if (os::is_MP()) {
-    if (UseMembar) {
-      // Force this write out before the read below
-      __ dmb(Assembler::ISH);
-    } else {
-      // Write serialization page so VM thread can do a pseudo remote membar.
-      // We use the current thread pointer to calculate a thread specific
-      // offset to write to within the page. This minimizes bus traffic
-      // due to cache line collision.
-      __ serialize_memory(rthread, rscratch2);
-    }
+  if (UseMembar) {
+    // Force this write out before the read below
+    __ dmb(Assembler::ISH);
+  } else {
+    // Write serialization page so VM thread can do a pseudo remote membar.
+    // We use the current thread pointer to calculate a thread specific
+    // offset to write to within the page. This minimizes bus traffic
+    // due to cache line collision.
+    __ serialize_memory(rthread, rscratch2);
   }
 
   // check for safepoint operation in progress and/or pending suspend requests

src/hotspot/cpu/arm/arm.ad

@@ -5316,8 +5316,7 @@ instruct loadConD(regD dst, immD src, iRegP tmp) %{
 // Prefetch instructions.
 // Must be safe to execute with invalid address (cannot fault).
 
-instruct prefetchAlloc_mp( memoryP mem ) %{
-  predicate(os::is_MP());
+instruct prefetchAlloc( memoryP mem ) %{
   match( PrefetchAllocation mem );
   ins_cost(MEMORY_REF_COST);
   size(4);
@@ -5333,23 +5332,6 @@ instruct prefetchAlloc_mp( memoryP mem ) %{
   ins_pipe(iload_mem);
 %}
 
-instruct prefetchAlloc_sp( memoryP mem ) %{
-  predicate(!os::is_MP());
-  match( PrefetchAllocation mem );
-  ins_cost(MEMORY_REF_COST);
-  size(4);
-
-  format %{ "PLD $mem\t! Prefetch allocation" %}
-  ins_encode %{
-#ifdef AARCH64
-    __ prfm(pstl1keep, $mem$$Address);
-#else
-    __ pld($mem$$Address);
-#endif
-  %}
-  ins_pipe(iload_mem);
-%}
-
 //----------Store Instructions-------------------------------------------------
 // Store Byte
 instruct storeB(memoryB mem, store_RegI src) %{

src/hotspot/cpu/arm/compiledIC_arm.cpp

@@ -155,9 +155,7 @@ void CompiledDirectStaticCall::set_stub_to_clean(static_stub_Relocation* static_
 void CompiledDirectStaticCall::verify() {
   // Verify call.
   _call->verify();
-  if (os::is_MP()) {
-    _call->verify_alignment();
-  }
+  _call->verify_alignment();
 
   // Verify stub.
   address stub = find_stub(/*is_aot*/ false);

src/hotspot/cpu/arm/jniFastGetField_arm.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -127,13 +127,9 @@ address JNI_FastGetField::generate_fast_get_int_field0(BasicType type) {
   __ bic(R1, R1, JNIHandles::weak_tag_mask);
 #endif
 
-  if (os::is_MP()) {
-    // Address dependency restricts memory access ordering. It's cheaper than explicit LoadLoad barrier
-    __ andr(Rtmp1, Rsafept_cnt, (unsigned)1);
-    __ ldr(Robj, Address(R1, Rtmp1));
-  } else {
-    __ ldr(Robj, Address(R1));
-  }
+  // Address dependency restricts memory access ordering. It's cheaper than explicit LoadLoad barrier
+  __ andr(Rtmp1, Rsafept_cnt, (unsigned)1);
+  __ ldr(Robj, Address(R1, Rtmp1));
 
 #ifdef AARCH64
   __ add(Robj, Robj, AsmOperand(R2, lsr, 2));
@@ -198,25 +194,21 @@ address JNI_FastGetField::generate_fast_get_int_field0(BasicType type) {
       ShouldNotReachHere();
   }
 
-  if(os::is_MP()) {
-      // Address dependency restricts memory access ordering. It's cheaper than explicit LoadLoad barrier
+  // Address dependency restricts memory access ordering. It's cheaper than explicit LoadLoad barrier
 #if defined(__ABI_HARD__) && !defined(AARCH64)
-    if (type == T_FLOAT || type == T_DOUBLE) {
-      __ ldr_literal(Rsafepoint_counter_addr, safepoint_counter_addr);
-      __ fmrrd(Rres, Rres_hi, D0);
-      __ eor(Rtmp2, Rres, Rres);
-      __ ldr_s32(Rsafept_cnt2, Address(Rsafepoint_counter_addr, Rtmp2));
-    } else
+  if (type == T_FLOAT || type == T_DOUBLE) {
+    __ ldr_literal(Rsafepoint_counter_addr, safepoint_counter_addr);
+    __ fmrrd(Rres, Rres_hi, D0);
+    __ eor(Rtmp2, Rres, Rres);
+    __ ldr_s32(Rsafept_cnt2, Address(Rsafepoint_counter_addr, Rtmp2));
+  } else
 #endif // __ABI_HARD__ && !AARCH64
-    {
+  {
 #ifndef AARCH64
-      __ ldr_literal(Rsafepoint_counter_addr, safepoint_counter_addr);
+    __ ldr_literal(Rsafepoint_counter_addr, safepoint_counter_addr);
 #endif // !AARCH64
-      __ eor(Rtmp2, Rres, Rres);
-      __ ldr_s32(Rsafept_cnt2, Address(Rsafepoint_counter_addr, Rtmp2));
-    }
-  } else {
-    __ ldr_s32(Rsafept_cnt2, Address(Rsafepoint_counter_addr));
+    __ eor(Rtmp2, Rres, Rres);
+    __ ldr_s32(Rsafept_cnt2, Address(Rsafepoint_counter_addr, Rtmp2));
   }
   __ cmp(Rsafept_cnt2, Rsafept_cnt);
 #ifdef AARCH64

src/hotspot/cpu/arm/macroAssembler_arm.cpp

@@ -1563,8 +1563,6 @@ FixedSizeCodeBlock::~FixedSizeCodeBlock() {
 // Serializes memory.
 // tmp register is not used on AArch64, this parameter is provided solely for better compatibility with 32-bit ARM
 void MacroAssembler::membar(Membar_mask_bits order_constraint, Register tmp) {
-  if (!os::is_MP()) return;
-
   // TODO-AARCH64 investigate dsb vs dmb effects
   if (order_constraint == StoreStore) {
     dmb(DMB_st);
@@ -1585,7 +1583,6 @@ void MacroAssembler::membar(Membar_mask_bits order_constraint,
                             Register tmp,
                             bool preserve_flags,
                             Register load_tgt) {
-  if (!os::is_MP()) return;
 
   if (order_constraint == StoreStore) {
     dmb(DMB_st, tmp);