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Dong BoRealFYang
Dong Bo
authored and
RealFYang
committed
8256318: AArch64: Add support for floating-point absolute difference
Reviewed-by: aph
1 parent 655bb61 commit b0b9dd2

24 files changed

+682
-456
lines changed

‎src/hotspot/cpu/aarch64/aarch64-asmtest.py

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1334,10 +1334,9 @@ def generate(kind, names):
13341334
["maddw", "msubw", "madd", "msub", "smaddl", "smsubl", "umaddl", "umsubl"])
13351335

13361336
generate(ThreeRegFloatOp,
1337-
[["fmuls", "sss"], ["fdivs", "sss"], ["fadds", "sss"], ["fsubs", "sss"],
1338-
["fmuls", "sss"],
1339-
["fmuld", "ddd"], ["fdivd", "ddd"], ["faddd", "ddd"], ["fsubd", "ddd"],
1340-
["fmuld", "ddd"]])
1337+
[["fabds", "sss"], ["fmuls", "sss"], ["fdivs", "sss"], ["fadds", "sss"], ["fsubs", "sss"],
1338+
["fabdd", "ddd"], ["fmuld", "ddd"], ["fdivd", "ddd"], ["faddd", "ddd"], ["fsubd", "ddd"],
1339+
])
13411340

13421341
generate(FourRegFloatOp,
13431342
[["fmadds", "ssss"], ["fmsubs", "ssss"], ["fnmadds", "ssss"], ["fnmadds", "ssss"],
@@ -1437,6 +1436,8 @@ def generate(kind, names):
14371436
["mulv", "mul", "8B"], ["mulv", "mul", "16B"],
14381437
["mulv", "mul", "4H"], ["mulv", "mul", "8H"],
14391438
["mulv", "mul", "2S"], ["mulv", "mul", "4S"],
1439+
["fabd", "fabd", "2S"], ["fabd", "fabd", "4S"],
1440+
["fabd", "fabd", "2D"],
14401441
["fmul", "fmul", "2S"], ["fmul", "fmul", "4S"],
14411442
["fmul", "fmul", "2D"],
14421443
["mlav", "mla", "4H"], ["mlav", "mla", "8H"],

‎src/hotspot/cpu/aarch64/aarch64.ad

Lines changed: 28 additions & 123 deletions
Original file line numberDiff line numberDiff line change
@@ -13894,6 +13894,34 @@ instruct absD_reg(vRegD dst, vRegD src) %{
1389413894
ins_pipe(fp_uop_d);
1389513895
%}
1389613896

13897+
instruct absdF_reg(vRegF dst, vRegF src1, vRegF src2) %{
13898+
match(Set dst (AbsF (SubF src1 src2)));
13899+
13900+
ins_cost(INSN_COST * 3);
13901+
format %{ "fabds $dst, $src1, $src2" %}
13902+
ins_encode %{
13903+
__ fabds(as_FloatRegister($dst$$reg),
13904+
as_FloatRegister($src1$$reg),
13905+
as_FloatRegister($src2$$reg));
13906+
%}
13907+
13908+
ins_pipe(fp_uop_s);
13909+
%}
13910+
13911+
instruct absdD_reg(vRegD dst, vRegD src1, vRegD src2) %{
13912+
match(Set dst (AbsD (SubD src1 src2)));
13913+
13914+
ins_cost(INSN_COST * 3);
13915+
format %{ "fabdd $dst, $src1, $src2" %}
13916+
ins_encode %{
13917+
__ fabdd(as_FloatRegister($dst$$reg),
13918+
as_FloatRegister($src1$$reg),
13919+
as_FloatRegister($src2$$reg));
13920+
%}
13921+
13922+
ins_pipe(fp_uop_d);
13923+
%}
13924+
1389713925
instruct sqrtD_reg(vRegD dst, vRegD src) %{
1389813926
match(Set dst (SqrtD src));
1389913927

@@ -17872,129 +17900,6 @@ instruct vsqrt2D(vecX dst, vecX src)
1787217900
ins_pipe(vsqrt_fp128);
1787317901
%}
1787417902

17875-
// --------------------------------- ABS --------------------------------------
17876-
17877-
instruct vabs8B(vecD dst, vecD src)
17878-
%{
17879-
predicate(n->as_Vector()->length() == 4 ||
17880-
n->as_Vector()->length() == 8);
17881-
match(Set dst (AbsVB src));
17882-
ins_cost(INSN_COST);
17883-
format %{ "abs $dst, $src\t# vector (8B)" %}
17884-
ins_encode %{
17885-
__ absr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg));
17886-
%}
17887-
ins_pipe(vlogical64);
17888-
%}
17889-
17890-
instruct vabs16B(vecX dst, vecX src)
17891-
%{
17892-
predicate(n->as_Vector()->length() == 16);
17893-
match(Set dst (AbsVB src));
17894-
ins_cost(INSN_COST);
17895-
format %{ "abs $dst, $src\t# vector (16B)" %}
17896-
ins_encode %{
17897-
__ absr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($src$$reg));
17898-
%}
17899-
ins_pipe(vlogical128);
17900-
%}
17901-
17902-
instruct vabs4S(vecD dst, vecD src)
17903-
%{
17904-
predicate(n->as_Vector()->length() == 4);
17905-
match(Set dst (AbsVS src));
17906-
ins_cost(INSN_COST);
17907-
format %{ "abs $dst, $src\t# vector (4H)" %}
17908-
ins_encode %{
17909-
__ absr(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg));
17910-
%}
17911-
ins_pipe(vlogical64);
17912-
%}
17913-
17914-
instruct vabs8S(vecX dst, vecX src)
17915-
%{
17916-
predicate(n->as_Vector()->length() == 8);
17917-
match(Set dst (AbsVS src));
17918-
ins_cost(INSN_COST);
17919-
format %{ "abs $dst, $src\t# vector (8H)" %}
17920-
ins_encode %{
17921-
__ absr(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg));
17922-
%}
17923-
ins_pipe(vlogical128);
17924-
%}
17925-
17926-
instruct vabs2I(vecD dst, vecD src)
17927-
%{
17928-
predicate(n->as_Vector()->length() == 2);
17929-
match(Set dst (AbsVI src));
17930-
ins_cost(INSN_COST);
17931-
format %{ "abs $dst, $src\t# vector (2S)" %}
17932-
ins_encode %{
17933-
__ absr(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg));
17934-
%}
17935-
ins_pipe(vlogical64);
17936-
%}
17937-
17938-
instruct vabs4I(vecX dst, vecX src)
17939-
%{
17940-
predicate(n->as_Vector()->length() == 4);
17941-
match(Set dst (AbsVI src));
17942-
ins_cost(INSN_COST);
17943-
format %{ "abs $dst, $src\t# vector (4S)" %}
17944-
ins_encode %{
17945-
__ absr(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
17946-
%}
17947-
ins_pipe(vlogical128);
17948-
%}
17949-
17950-
instruct vabs2L(vecX dst, vecX src)
17951-
%{
17952-
predicate(n->as_Vector()->length() == 2);
17953-
match(Set dst (AbsVL src));
17954-
ins_cost(INSN_COST);
17955-
format %{ "abs $dst, $src\t# vector (2D)" %}
17956-
ins_encode %{
17957-
__ absr(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg));
17958-
%}
17959-
ins_pipe(vlogical128);
17960-
%}
17961-
17962-
instruct vabs2F(vecD dst, vecD src)
17963-
%{
17964-
predicate(n->as_Vector()->length() == 2);
17965-
match(Set dst (AbsVF src));
17966-
ins_cost(INSN_COST * 3);
17967-
format %{ "fabs $dst,$src\t# vector (2S)" %}
17968-
ins_encode %{
17969-
__ fabs(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg));
17970-
%}
17971-
ins_pipe(vunop_fp64);
17972-
%}
17973-
17974-
instruct vabs4F(vecX dst, vecX src)
17975-
%{
17976-
predicate(n->as_Vector()->length() == 4);
17977-
match(Set dst (AbsVF src));
17978-
ins_cost(INSN_COST * 3);
17979-
format %{ "fabs $dst,$src\t# vector (4S)" %}
17980-
ins_encode %{
17981-
__ fabs(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
17982-
%}
17983-
ins_pipe(vunop_fp128);
17984-
%}
17985-
17986-
instruct vabs2D(vecX dst, vecX src)
17987-
%{
17988-
predicate(n->as_Vector()->length() == 2);
17989-
match(Set dst (AbsVD src));
17990-
ins_cost(INSN_COST * 3);
17991-
format %{ "fabs $dst,$src\t# vector (2D)" %}
17992-
ins_encode %{
17993-
__ fabs(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg));
17994-
%}
17995-
ins_pipe(vunop_fp128);
17996-
%}
17997-
1799817903
// --------------------------------- NEG --------------------------------------
1799917904

1800017905
instruct vneg2F(vecD dst, vecD src)

‎src/hotspot/cpu/aarch64/aarch64_neon.ad

Lines changed: 163 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3454,3 +3454,166 @@ instruct alltrue_in_mask16B(iRegINoSp dst, vecX src1, vecX src2, vecX tmp, rFlag
34543454
%}
34553455
ins_pipe(pipe_slow);
34563456
%}
3457+
3458+
// --------------------------------- ABS --------------------------------------
3459+
3460+
instruct vabs8B(vecD dst, vecD src)
3461+
%{
3462+
predicate(n->as_Vector()->length() == 4 || n->as_Vector()->length() == 8);
3463+
match(Set dst (AbsVB src));
3464+
ins_cost(INSN_COST);
3465+
format %{ "abs $dst, $src\t# vector (8B)" %}
3466+
ins_encode %{
3467+
__ absr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg));
3468+
%}
3469+
ins_pipe(vlogical64);
3470+
%}
3471+
3472+
instruct vabs16B(vecX dst, vecX src)
3473+
%{
3474+
predicate(n->as_Vector()->length() == 16);
3475+
match(Set dst (AbsVB src));
3476+
ins_cost(INSN_COST);
3477+
format %{ "abs $dst, $src\t# vector (16B)" %}
3478+
ins_encode %{
3479+
__ absr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($src$$reg));
3480+
%}
3481+
ins_pipe(vlogical128);
3482+
%}
3483+
3484+
instruct vabs4S(vecD dst, vecD src)
3485+
%{
3486+
predicate(n->as_Vector()->length() == 4);
3487+
match(Set dst (AbsVS src));
3488+
ins_cost(INSN_COST);
3489+
format %{ "abs $dst, $src\t# vector (4H)" %}
3490+
ins_encode %{
3491+
__ absr(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg));
3492+
%}
3493+
ins_pipe(vlogical64);
3494+
%}
3495+
3496+
instruct vabs8S(vecX dst, vecX src)
3497+
%{
3498+
predicate(n->as_Vector()->length() == 8);
3499+
match(Set dst (AbsVS src));
3500+
ins_cost(INSN_COST);
3501+
format %{ "abs $dst, $src\t# vector (8H)" %}
3502+
ins_encode %{
3503+
__ absr(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg));
3504+
%}
3505+
ins_pipe(vlogical128);
3506+
%}
3507+
3508+
instruct vabs2I(vecD dst, vecD src)
3509+
%{
3510+
predicate(n->as_Vector()->length() == 2);
3511+
match(Set dst (AbsVI src));
3512+
ins_cost(INSN_COST);
3513+
format %{ "abs $dst, $src\t# vector (2S)" %}
3514+
ins_encode %{
3515+
__ absr(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg));
3516+
%}
3517+
ins_pipe(vlogical64);
3518+
%}
3519+
3520+
instruct vabs4I(vecX dst, vecX src)
3521+
%{
3522+
predicate(n->as_Vector()->length() == 4);
3523+
match(Set dst (AbsVI src));
3524+
ins_cost(INSN_COST);
3525+
format %{ "abs $dst, $src\t# vector (4S)" %}
3526+
ins_encode %{
3527+
__ absr(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
3528+
%}
3529+
ins_pipe(vlogical128);
3530+
%}
3531+
3532+
instruct vabs2L(vecX dst, vecX src)
3533+
%{
3534+
predicate(n->as_Vector()->length() == 2);
3535+
match(Set dst (AbsVL src));
3536+
ins_cost(INSN_COST);
3537+
format %{ "abs $dst, $src\t# vector (2D)" %}
3538+
ins_encode %{
3539+
__ absr(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg));
3540+
%}
3541+
ins_pipe(vlogical128);
3542+
%}
3543+
3544+
instruct vabs2F(vecD dst, vecD src)
3545+
%{
3546+
predicate(n->as_Vector()->length() == 2);
3547+
match(Set dst (AbsVF src));
3548+
ins_cost(INSN_COST * 3);
3549+
format %{ "fabs $dst, $src\t# vector (2S)" %}
3550+
ins_encode %{
3551+
__ fabs(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg));
3552+
%}
3553+
ins_pipe(vunop_fp64);
3554+
%}
3555+
3556+
instruct vabs4F(vecX dst, vecX src)
3557+
%{
3558+
predicate(n->as_Vector()->length() == 4);
3559+
match(Set dst (AbsVF src));
3560+
ins_cost(INSN_COST * 3);
3561+
format %{ "fabs $dst, $src\t# vector (4S)" %}
3562+
ins_encode %{
3563+
__ fabs(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
3564+
%}
3565+
ins_pipe(vunop_fp128);
3566+
%}
3567+
3568+
instruct vabs2D(vecX dst, vecX src)
3569+
%{
3570+
predicate(n->as_Vector()->length() == 2);
3571+
match(Set dst (AbsVD src));
3572+
ins_cost(INSN_COST * 3);
3573+
format %{ "fabs $dst, $src\t# vector (2D)" %}
3574+
ins_encode %{
3575+
__ fabs(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg));
3576+
%}
3577+
ins_pipe(vunop_fp128);
3578+
%}
3579+
3580+
// --------------------------------- FABS DIFF --------------------------------
3581+
3582+
instruct vabd2F(vecD dst, vecD src1, vecD src2)
3583+
%{
3584+
predicate(n->as_Vector()->length() == 2);
3585+
match(Set dst (AbsVF (SubVF src1 src2)));
3586+
ins_cost(INSN_COST * 3);
3587+
format %{ "fabd $dst, $src1, $src2\t# vector (2S)" %}
3588+
ins_encode %{
3589+
__ fabd(as_FloatRegister($dst$$reg), __ T2S,
3590+
as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
3591+
%}
3592+
ins_pipe(vunop_fp64);
3593+
%}
3594+
3595+
instruct vabd4F(vecX dst, vecX src1, vecX src2)
3596+
%{
3597+
predicate(n->as_Vector()->length() == 4);
3598+
match(Set dst (AbsVF (SubVF src1 src2)));
3599+
ins_cost(INSN_COST * 3);
3600+
format %{ "fabd $dst, $src1, $src2\t# vector (4S)" %}
3601+
ins_encode %{
3602+
__ fabd(as_FloatRegister($dst$$reg), __ T4S,
3603+
as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
3604+
%}
3605+
ins_pipe(vunop_fp128);
3606+
%}
3607+
3608+
instruct vabd2D(vecX dst, vecX src1, vecX src2)
3609+
%{
3610+
predicate(n->as_Vector()->length() == 2);
3611+
match(Set dst (AbsVD (SubVD src1 src2)));
3612+
ins_cost(INSN_COST * 3);
3613+
format %{ "fabd $dst, $src1, $src2\t# vector (2D)" %}
3614+
ins_encode %{
3615+
__ fabd(as_FloatRegister($dst$$reg), __ T2D,
3616+
as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
3617+
%}
3618+
ins_pipe(vunop_fp128);
3619+
%}

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