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Commit 04cd0ac

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author
duke
committed
Automatic merge of jdk:master into master
2 parents 2ad1e86 + 67a9590 commit 04cd0ac

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3 files changed

+108
-59
lines changed

3 files changed

+108
-59
lines changed

‎src/hotspot/cpu/aarch64/aarch64_sve.ad

Lines changed: 49 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -101,6 +101,27 @@ source %{
101101
return vt->element_basic_type();
102102
}
103103

104+
static Assembler::SIMD_RegVariant elemBytes_to_regVariant(int esize) {
105+
switch(esize) {
106+
case 1:
107+
return Assembler::B;
108+
case 2:
109+
return Assembler::H;
110+
case 4:
111+
return Assembler::S;
112+
case 8:
113+
return Assembler::D;
114+
default:
115+
assert(false, "unsupported");
116+
ShouldNotReachHere();
117+
}
118+
return Assembler::INVALID;
119+
}
120+
121+
static Assembler::SIMD_RegVariant elemType_to_regVariant(BasicType bt) {
122+
return elemBytes_to_regVariant(type2aelembytes(bt));
123+
}
124+
104125
typedef void (C2_MacroAssembler::* sve_mem_insn_predicate)(FloatRegister Rt, Assembler::SIMD_RegVariant T,
105126
PRegister Pg, const Address &adr);
106127

@@ -464,56 +485,44 @@ instruct vdivD(vReg dst_src1, vReg src2) %{
464485
ins_pipe(pipe_slow);
465486
%}
466487

467-
// vector max
468-
469-
instruct vmaxF(vReg dst_src1, vReg src2) %{
470-
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4 &&
471-
n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
472-
match(Set dst_src1 (MaxV dst_src1 src2));
473-
ins_cost(SVE_COST);
474-
format %{ "sve_fmax $dst_src1, $dst_src1, $src2\t # vector (sve) (S)" %}
475-
ins_encode %{
476-
__ sve_fmax(as_FloatRegister($dst_src1$$reg), __ S,
477-
ptrue, as_FloatRegister($src2$$reg));
478-
%}
479-
ins_pipe(pipe_slow);
480-
%}
481-
482-
instruct vmaxD(vReg dst_src1, vReg src2) %{
483-
predicate(UseSVE > 0 && n->as_Vector()->length() >= 2 &&
484-
n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
485-
match(Set dst_src1 (MaxV dst_src1 src2));
486-
ins_cost(SVE_COST);
487-
format %{ "sve_fmax $dst_src1, $dst_src1, $src2\t # vector (sve) (D)" %}
488-
ins_encode %{
489-
__ sve_fmax(as_FloatRegister($dst_src1$$reg), __ D,
490-
ptrue, as_FloatRegister($src2$$reg));
491-
%}
492-
ins_pipe(pipe_slow);
493-
%}
488+
// vector min/max
494489

495-
instruct vminF(vReg dst_src1, vReg src2) %{
496-
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4 &&
497-
n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
490+
instruct vmin(vReg dst_src1, vReg src2) %{
491+
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
498492
match(Set dst_src1 (MinV dst_src1 src2));
499493
ins_cost(SVE_COST);
500-
format %{ "sve_fmin $dst_src1, $dst_src1, $src2\t # vector (sve) (S)" %}
494+
format %{ "sve_min $dst_src1, $dst_src1, $src2\t # vector (sve)" %}
501495
ins_encode %{
502-
__ sve_fmin(as_FloatRegister($dst_src1$$reg), __ S,
503-
ptrue, as_FloatRegister($src2$$reg));
496+
BasicType bt = vector_element_basic_type(this);
497+
Assembler::SIMD_RegVariant size = elemType_to_regVariant(bt);
498+
if (is_floating_point_type(bt)) {
499+
__ sve_fmin(as_FloatRegister($dst_src1$$reg), size,
500+
ptrue, as_FloatRegister($src2$$reg));
501+
} else {
502+
assert(is_integral_type(bt), "Unsupported type");
503+
__ sve_smin(as_FloatRegister($dst_src1$$reg), size,
504+
ptrue, as_FloatRegister($src2$$reg));
505+
}
504506
%}
505507
ins_pipe(pipe_slow);
506508
%}
507509

508-
instruct vminD(vReg dst_src1, vReg src2) %{
509-
predicate(UseSVE > 0 && n->as_Vector()->length() >= 2 &&
510-
n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
511-
match(Set dst_src1 (MinV dst_src1 src2));
510+
instruct vmax(vReg dst_src1, vReg src2) %{
511+
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
512+
match(Set dst_src1 (MaxV dst_src1 src2));
512513
ins_cost(SVE_COST);
513-
format %{ "sve_fmin $dst_src1, $dst_src1, $src2\t # vector (sve) (D)" %}
514+
format %{ "sve_max $dst_src1, $dst_src1, $src2\t # vector (sve)" %}
514515
ins_encode %{
515-
__ sve_fmin(as_FloatRegister($dst_src1$$reg), __ D,
516-
ptrue, as_FloatRegister($src2$$reg));
516+
BasicType bt = vector_element_basic_type(this);
517+
Assembler::SIMD_RegVariant size = elemType_to_regVariant(bt);
518+
if (is_floating_point_type(bt)) {
519+
__ sve_fmax(as_FloatRegister($dst_src1$$reg), size,
520+
ptrue, as_FloatRegister($src2$$reg));
521+
} else {
522+
assert(is_integral_type(bt), "Unsupported type");
523+
__ sve_smax(as_FloatRegister($dst_src1$$reg), size,
524+
ptrue, as_FloatRegister($src2$$reg));
525+
}
517526
%}
518527
ins_pipe(pipe_slow);
519528
%}

‎src/hotspot/cpu/aarch64/aarch64_sve_ad.m4

Lines changed: 58 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,27 @@ source %{
8888
return vt->element_basic_type();
8989
}
9090

91+
static Assembler::SIMD_RegVariant elemBytes_to_regVariant(int esize) {
92+
switch(esize) {
93+
case 1:
94+
return Assembler::B;
95+
case 2:
96+
return Assembler::H;
97+
case 4:
98+
return Assembler::S;
99+
case 8:
100+
return Assembler::D;
101+
default:
102+
assert(false, "unsupported");
103+
ShouldNotReachHere();
104+
}
105+
return Assembler::INVALID;
106+
}
107+
108+
static Assembler::SIMD_RegVariant elemType_to_regVariant(BasicType bt) {
109+
return elemBytes_to_regVariant(type2aelembytes(bt));
110+
}
111+
91112
typedef void (C2_MacroAssembler::* sve_mem_insn_predicate)(FloatRegister Rt, Assembler::SIMD_RegVariant T,
92113
PRegister Pg, const Address &adr);
93114

@@ -319,28 +340,47 @@ instruct vdiv$1(vReg dst_src1, vReg src2) %{
319340
VDIVF(F, S, 4)
320341
VDIVF(D, D, 2)
321342

322-
dnl
323-
dnl BINARY_OP_TRUE_PREDICATE_ETYPE($1, $2, $3, $4, $5, $6 )
324-
dnl BINARY_OP_TRUE_PREDICATE_ETYPE(insn_name, op_name, element_type, size, min_vec_len, insn)
325-
define(`BINARY_OP_TRUE_PREDICATE_ETYPE', `
326-
instruct $1(vReg dst_src1, vReg src2) %{
327-
predicate(UseSVE > 0 && n->as_Vector()->length() >= $5 &&
328-
n->bottom_type()->is_vect()->element_basic_type() == $3);
329-
match(Set dst_src1 ($2 dst_src1 src2));
343+
// vector min/max
344+
345+
instruct vmin(vReg dst_src1, vReg src2) %{
346+
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
347+
match(Set dst_src1 (MinV dst_src1 src2));
330348
ins_cost(SVE_COST);
331-
format %{ "$6 $dst_src1, $dst_src1, $src2\t # vector (sve) ($4)" %}
349+
format %{ "sve_min $dst_src1, $dst_src1, $src2\t # vector (sve)" %}
332350
ins_encode %{
333-
__ $6(as_FloatRegister($dst_src1$$reg), __ $4,
334-
ptrue, as_FloatRegister($src2$$reg));
351+
BasicType bt = vector_element_basic_type(this);
352+
Assembler::SIMD_RegVariant size = elemType_to_regVariant(bt);
353+
if (is_floating_point_type(bt)) {
354+
__ sve_fmin(as_FloatRegister($dst_src1$$reg), size,
355+
ptrue, as_FloatRegister($src2$$reg));
356+
} else {
357+
assert(is_integral_type(bt), "Unsupported type");
358+
__ sve_smin(as_FloatRegister($dst_src1$$reg), size,
359+
ptrue, as_FloatRegister($src2$$reg));
360+
}
335361
%}
336362
ins_pipe(pipe_slow);
337-
%}')dnl
338-
dnl
339-
// vector max
340-
BINARY_OP_TRUE_PREDICATE_ETYPE(vmaxF, MaxV, T_FLOAT, S, 4, sve_fmax)
341-
BINARY_OP_TRUE_PREDICATE_ETYPE(vmaxD, MaxV, T_DOUBLE, D, 2, sve_fmax)
342-
BINARY_OP_TRUE_PREDICATE_ETYPE(vminF, MinV, T_FLOAT, S, 4, sve_fmin)
343-
BINARY_OP_TRUE_PREDICATE_ETYPE(vminD, MinV, T_DOUBLE, D, 2, sve_fmin)
363+
%}
364+
365+
instruct vmax(vReg dst_src1, vReg src2) %{
366+
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
367+
match(Set dst_src1 (MaxV dst_src1 src2));
368+
ins_cost(SVE_COST);
369+
format %{ "sve_max $dst_src1, $dst_src1, $src2\t # vector (sve)" %}
370+
ins_encode %{
371+
BasicType bt = vector_element_basic_type(this);
372+
Assembler::SIMD_RegVariant size = elemType_to_regVariant(bt);
373+
if (is_floating_point_type(bt)) {
374+
__ sve_fmax(as_FloatRegister($dst_src1$$reg), size,
375+
ptrue, as_FloatRegister($src2$$reg));
376+
} else {
377+
assert(is_integral_type(bt), "Unsupported type");
378+
__ sve_smax(as_FloatRegister($dst_src1$$reg), size,
379+
ptrue, as_FloatRegister($src2$$reg));
380+
}
381+
%}
382+
ins_pipe(pipe_slow);
383+
%}
344384

345385
dnl
346386
dnl VFMLA($1 $2 $3 )

‎src/hotspot/cpu/aarch64/assembler_aarch64.hpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1534,7 +1534,7 @@ class Assembler : public AbstractAssembler {
15341534
};
15351535

15361536
enum SIMD_RegVariant {
1537-
B, H, S, D, Q
1537+
B, H, S, D, Q, INVALID
15381538
};
15391539

15401540
enum shift_kind { LSL, LSR, ASR, ROR };

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