readme: Update docs on CACHE WIDTH option

[stffrdhrn]

As discussed in IRC:

  12:39 < stekern> oetwi_: or1k can only dynamically control addresses to
        be cacheable/noncacheable when the mmu is enabled.
  12:40 < stekern> mor1kx have an option to work around this, you can
        hardwire the upper address space to be noncacheable by adjusting
        OPTION_DCACHE_LIMIT_WIDTH
  12:42 < stekern> (we should fix the linux kernel to setup some mmu
        mapping that marks the uart as non-cacheable before the first early
        prints)

We have traditionally set cache address width to 31 and mapped devices
into high order address space to avoid caching of device reads and
writes. Add this as a recommendation in the mor1kx options
documentation.