sipeed/m1s-dock: use critical-section

For now, switch to a forked and patch bl808-pac. PR pending:
bouffalolab/bl808-pac#5

Signed-off-by: Daniel Maslowski <info@orangecms.org>

src/mainboard/sipeed/m1s-dock/e907/Cargo.toml

@@ -9,8 +9,10 @@ authors = [
 edition = "2021"
 
 [dependencies]
+bl808-pac = { git = "https://github.com/orangecms/bl808-pac", branch = "main", features = ["rt", "critical-section"] }
+critical-section = "1.0"
 embedded-hal = "=1.0.0-alpha.8"
 nb = "1"
-riscv = "0.9.0"
+riscv = { version = "0.10.1", features = ["critical-section-single-hart"] }
+riscv-rt = "0.11.0"
 spin = "0.9"
-bl808-pac = "0.0.0"

src/mainboard/sipeed/m1s-dock/e907/src/main.rs

@@ -88,28 +88,26 @@ fn riscv_plat_info() {
  * the D0 core (64-bit "MM"/multimedia) otherwise.
  */
 fn main() {
-    unsafe {
-        let p = Peripherals::steal();
-        let glb = p.GLB;
-        init::gpio_uart_init(&glb);
-        let serial = init::BSerial::new(p.UART0, p.UART1);
-        log::set_logger(serial);
+    let p = Peripherals::take().unwrap();
+    let glb = p.GLB;
+    init::gpio_uart_init(&glb);
+    let serial = init::BSerial::new(p.UART0, p.UART1);
+    log::set_logger(serial);
 
-        // print to UART0
-        log::_debug(42);
+    // print to UART0
+    log::_debug(42);
 
-        // prints to UART1
-        println!("oreboot 🦀");
-        riscv_plat_info();
-        println!("{}", glb.chip_inform.read().bits());
+    // prints to UART1
+    println!("oreboot 🦀");
+    riscv_plat_info();
+    println!("{}", glb.chip_inform.read().bits());
 
-        for _ in 0..4 {
-            println!("🐢");
-            sleep();
-        }
-        init::resume_mm();
-        init::reset_cpu();
+    for _ in 0..4 {
+        println!("🐢");
+        sleep();
     }
+    init::resume_mm();
+    init::reset_cpu();
 }
 
 #[cfg_attr(not(test), panic_handler)]