Running MicroPython on an asymmetric RISC-V coprocessor (XuanTie E906) next to Linux

[tcmichals]

This project implements an asymmetric multiprocessing (AMP) architecture on the Allwinner T527 to execute MicroPython on an isolated 200 MHz XuanTie E906 RISC-V coprocessor alongside host Linux ARM Cortex-A55 cores. Interactive REPL bridging, script injection, and host instrumentation operate over a zero-copy VirtIO/RPMsg layer using shared SRAM ring buffers and hardware message box doorbells. To prevent the typical 5–15ms mark-and-sweep garbage collection freezes that break real-time sensor loops, uasyncio was bypassed for a static generator coroutine pattern that yields execution directly to hardware interrupt sleep (wfi) with zero steady-state heap allocations. High-rate 115,200 baud streams utilize a circular UART receive DMA ring paired with the hardware character timeout interrupt (IIR = 0x0C) to safely flush trailing data into Python, providing ample headroom against unexpected processing gaps.
Full technical details, device tree overlays (.dtbo), and silicon benchmarks are documented here:
https://allthingsembedded.blogspot.com/2026/10/micropython-on-e906t527-on-cubie-ae5.html