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BCD-to-7-SEGMENT-using-Verilog-
BCD-to-7-SEGMENT-using-Verilog- PublicThis repository contains verilog code used to implment a BCD to 7 segment display. This implementation is done using gate level modeling as well as behavioral modelling.
Verilog
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PSoC_robot
PSoC_robot PublicThis repository contains the source code of a task specific robot created using a Cypress PSoC. The code is written in C++ and the functions of the robot has been implemented using internal and ext…
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The-Green-Machine
The-Green-Machine PublicThe GitHub repository of Team AP116 in the InnovateFPGA Design Contest 2021/22
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