Verilog Testbench Generator

Custom verilog test-bench skeleton generator written in C++ to make our lives simpler.

Why?

Student usually start their verilog journey with tools like Xilinx ISE, and these ide/tools have the options of generating testbenches and creating modules using graphical tools. Unfortunately, for student shifting to iVerilog and other open-source tools (Even Vivado), these options don't exist. So to make it a little easier for the students, this program was created.

Isn't learning syntax for TB better?

Yes it is. But then again, this is FOR BEGINNERS. To start at the shallow end.

License : GNU GPL v3

Happy Tinkerin' !