Verilog attribute parsing OpenSTA

[QuantamHD]

Allows STA to read, parse and write verilog attributes, example below.

/* Generated by Yosys 0.8+ */

(* hdlname = "\\counter" *)
(* top =  1  *)
(* src = "synthesis/tests/counter.v:16.1-32.10" *)
module counter(clk, reset, out);
  wire _0000_;
  wire _0001_;

[CLAassistant]

All committers have signed the CLA.

[QuantamHD]

Thanks for the feedback.

Addressed all comments. After moving to std::string I needed to wrap it in std::optional in order to preserve an unset value check.

I the new API overall, but if you don't we can go back to const char * or return an empty std::string when the attribute is not found.

[jjcherry56]

I am having a hard time seeing a reason to distinguish between an empty string and a missing value. I don't think the std::optional is very useful here. Please use a "using" to get rid of all the std::'s. I think string is already covered by StringUtil.hh

[QuantamHD]

I think the question is, is this a valid attribute (* src="" *), and if it is can an API user differentiate between (* src="" *) and (**). The optional would be empty in the latter, but not the former.

I think I tend to agree with you though. It seems like in most other place we don't differentiate between empty string and not present. I'll go back to just string

[QuantamHD]

All feedback has been addressed.

[jjcherry56]

ship it

[QuantamHD]

Cool, Merge whenever you're ready. I don't have any permission on this repo

[akashlevy]

Hey Ethan @QuantamHD ,

I am finding that this PR results in a parsing error when >2 attributes are present on a line:

netlist.v line 1520, syntax error, unexpected ',', expecting ATTRIBUTE_CLOSED

To reproduce, try a multi-attribute statement like: (* src = "design.v:1.1-2.1", test1 = "test1", test2 = "test2" *)