S2 PLLs

Registers

These registers control the speed of the DDR memory on the S2 SoC. They are located on PCI Bar 0. The default speed for the MacBook Air 6,2 is 450MHz.

0:0x04

PLL reference clock. Can be set to 24 or 25 MHz.

• Written with values: none
• Bit 3: 0 = 24MHz, 1 = 25MHz

0:0x14

Register is written with value 0x3 after sleeping for 10ms on a soft s2 PLL reset.

• Written with values: 0x3

0:0x20

PLL settings for 24MHz refclock

• Written to values: 0x03200000 (for all clock speeds)

0:0x24

PLL settings for both 24MHz and 25MHz

• Written to values:
• 200MHz @ 24MHz: 0x14280c06
• 200MHz @ 25MHz: 0x19281008
• 300MHz @ 24MHz: 0x14280804
• 300MHz @ 25MHz: 0x19280c06
• 400MHz @ 24MHz: 0x14280603
• 400MHz @ 25MHz: 0x19280804
• 450MHz @ 24MHz: 0x14280904
• 450MHz @ 25MHz: 0x19280904

0:0x2c

Used during PLL reset sequence.

• Written to values: 0x0, 0x40

0:0x9c

Used for DDR PHY soft reset sequence.

• Written to values: 0xffbff, 0xfffff

0:0xa8

Used for DDR PHY soft reset sequence.

• Written to values: 0x281

0:0x100

Used during PLL reset

• Written to values: 0xbcbc1500

0:0x510

PLL settings for 25MHz

• Written to values:
• 200MHz: 0x00400078
• 300MHz: 0x00480078
• 400MHz: 0x00400078
• 450MHz: 0x0048007d

S2 PLL soft reset logic

• Write 0x40 to 0:0x2c
• Write 0x0 to 0:0x2c
• Write 0xbcbc1500 to 0:0x100
• Write 0x0 to 0:0x14
• Wait for 10ms
• Write 0x3 to 0:0x14

S2 DDR PHY soft reset logic

• Write 0x281 to 0:0xa8
• Write 0xfffff to 0:0x9c
• Wait for 10ms
• Write 0xffbff to 0:0x9c