Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[FromVerilog] Add support for netlists in Pyverilog importer #1186

Draft
wants to merge 15 commits into
base: master
Choose a base branch
from

Conversation

Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant