@@ -561,7 +561,7 @@ int ir_get_target_constraints(ir_ctx *ctx, ir_ref ref, ir_target_constraints *co
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n++;
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}
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}
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- flags = IR_USE_SHOULD_BE_IN_REG | IR_OP2_SHOULD_BE_IN_REG | IR_OP3_SHOULD_BE_IN_REG;
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+ flags = IR_USE_SHOULD_BE_IN_REG | IR_OP2_MUST_BE_IN_REG | IR_OP3_SHOULD_BE_IN_REG;
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break;
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case IR_COND:
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insn = &ctx->ir_base[ref];
@@ -3953,6 +3953,10 @@ static void ir_emit_alloca(ir_ctx *ctx, ir_ref def, ir_insn *insn)
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dasm_State **Dst = &data->dasm_state;
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ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
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+ if (ctx->use_lists[def].count == 1) {
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+ /* dead alloca */
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+ return;
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+ }
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if (IR_IS_CONST_REF(insn->op2)) {
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ir_insn *val = &ctx->ir_base[insn->op2];
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int32_t size = val->val.i32;
@@ -4314,16 +4318,18 @@ static void ir_emit_switch(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn)
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}
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}
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- if (aarch64_may_encode_imm12(max.i64)) {
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- | ASM_REG_IMM_OP cmp, type, op2_reg, max.i64
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- } else {
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- ir_emit_load_imm_int(ctx, type, tmp_reg, max.i64);
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- | ASM_REG_REG_OP cmp, type, op2_reg, tmp_reg
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- }
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- if (IR_IS_TYPE_SIGNED(type)) {
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- | bgt =>default_label
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- } else {
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- | bhi =>default_label
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+ if (default_label) {
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+ if (aarch64_may_encode_imm12(max.i64)) {
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+ | ASM_REG_IMM_OP cmp, type, op2_reg, max.i64
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+ } else {
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+ ir_emit_load_imm_int(ctx, type, tmp_reg, max.i64);
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+ | ASM_REG_REG_OP cmp, type, op2_reg, tmp_reg
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+ }
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+ if (IR_IS_TYPE_SIGNED(type)) {
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+ | bgt =>default_label
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+ } else {
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+ | bhi =>default_label
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+ }
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}
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if (op1_reg == IR_REG_NONE) {
@@ -4335,11 +4341,15 @@ static void ir_emit_switch(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn)
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ir_emit_load_imm_int(ctx, type, tmp_reg, min.i64);
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| ASM_REG_REG_REG_OP subs, type, op1_reg, op2_reg, tmp_reg
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}
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- if (IR_IS_TYPE_SIGNED(type)) {
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- | blt =>default_label
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- } else {
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- | blo =>default_label
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+
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+ if (default_label) {
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+ if (IR_IS_TYPE_SIGNED(type)) {
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+ | blt =>default_label
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+ } else {
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+ | blo =>default_label
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+ }
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}
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+
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| adr Rx(tmp_reg), >1
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| ldr Rx(tmp_reg), [Rx(tmp_reg), Rx(op1_reg), lsl #3]
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| br Rx(tmp_reg)
@@ -4352,25 +4362,29 @@ static void ir_emit_switch(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn)
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|1:
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for (i = 0; i <= (max.i64 - min.i64); i++) {
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int b = labels[i];
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- ir_block *bb = &ctx->cfg_blocks[b];
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- ir_insn *insn = &ctx->ir_base[bb->end];
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-
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- if (insn->op == IR_IJMP && IR_IS_CONST_REF(insn->op2)) {
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- ir_ref prev = ctx->prev_ref[bb->end];
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- if (prev != bb->start && ctx->ir_base[prev].op == IR_SNAPSHOT) {
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- prev = ctx->prev_ref[prev];
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- }
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- if (prev == bb->start) {
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- void *addr = ir_jmp_addr(ctx, insn, &ctx->ir_base[insn->op2]);
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+ if (b) {
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+ ir_block *bb = &ctx->cfg_blocks[b];
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+ ir_insn *insn = &ctx->ir_base[bb->end];
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+
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+ if (insn->op == IR_IJMP && IR_IS_CONST_REF(insn->op2)) {
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+ ir_ref prev = ctx->prev_ref[bb->end];
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+ if (prev != bb->start && ctx->ir_base[prev].op == IR_SNAPSHOT) {
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+ prev = ctx->prev_ref[prev];
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+ }
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+ if (prev == bb->start) {
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+ void *addr = ir_jmp_addr(ctx, insn, &ctx->ir_base[insn->op2]);
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- | .addr &addr
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- if (ctx->ir_base[bb->start].op != IR_CASE_DEFAULT) {
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- bb->flags |= IR_BB_EMPTY;
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+ | .addr &addr
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+ if (ctx->ir_base[bb->start].op != IR_CASE_DEFAULT) {
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+ bb->flags |= IR_BB_EMPTY;
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+ }
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+ continue;
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}
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- continue;
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}
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+ | .addr =>b
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+ } else {
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+ | .addr 0
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}
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- | .addr =>b
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}
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|.code
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ir_mem_free(labels);
@@ -5187,7 +5201,9 @@ static void ir_emit_load_params(ir_ctx *ctx)
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dst_reg = IR_REG_NUM(ctx->regs[use][0]);
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IR_ASSERT(src_reg != IR_REG_NONE || dst_reg != IR_REG_NONE ||
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stack_offset == ctx->live_intervals[ctx->vregs[use]]->stack_spill_pos +
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- ((ctx->flags & IR_USE_FRAME_POINTER) ? -ctx->stack_frame_size : ctx->call_stack_size));
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+ ((ctx->flags & IR_USE_FRAME_POINTER) ?
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+ -(ctx->stack_frame_size - ctx->stack_frame_alignment) :
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+ ctx->call_stack_size));
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if (src_reg != dst_reg) {
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ir_emit_param_move(ctx, insn->type, src_reg, dst_reg, use, stack_offset);
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}
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