Skip to content

Commit e364af9

Browse files
dstogovdstogov
committed
Fixed allocated register clobbering
1 parent 1523733 commit e364af9

File tree

1 file changed

+47
-22
lines changed

1 file changed

+47
-22
lines changed

‎ext/opcache/jit/zend_jit_x86.dasc

Lines changed: 47 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -551,9 +551,9 @@ static void* dasm_labels[zend_lb_MAX];
551551
|| }
552552
|.endmacro
553553

554-
|.macro SSE_OP, sse_ins, reg, addr
554+
|.macro SSE_OP, sse_ins, reg, addr, tmp_reg
555555
|| if (Z_MODE(addr) == IS_CONST_ZVAL) {
556-
| MEM_OP2_2 sse_ins, xmm(reg-ZREG_XMM0), qword, Z_ZV(addr), r0
556+
| MEM_OP2_2 sse_ins, xmm(reg-ZREG_XMM0), qword, Z_ZV(addr), tmp_reg
557557
|| } else if (Z_MODE(addr) == IS_MEM_ZVAL) {
558558
| sse_ins xmm(reg-ZREG_XMM0), qword [Ra(Z_REG(addr))+Z_OFFSET(addr)]
559559
|| } else if (Z_MODE(addr) == IS_REG) {
@@ -658,19 +658,19 @@ static void* dasm_labels[zend_lb_MAX];
658658
|| }
659659
|.endmacro
660660

661-
|.macro SSE_MATH, opcode, reg, addr
661+
|.macro SSE_MATH, opcode, reg, addr, tmp_reg
662662
|| switch (opcode) {
663663
|| case ZEND_ADD:
664-
| SSE_OP addsd, reg, addr
664+
| SSE_OP addsd, reg, addr, tmp_reg
665665
|| break;
666666
|| case ZEND_SUB:
667-
| SSE_OP subsd, reg, addr
667+
| SSE_OP subsd, reg, addr, tmp_reg
668668
|| break;
669669
|| case ZEND_MUL:
670-
| SSE_OP mulsd, reg, addr
670+
| SSE_OP mulsd, reg, addr, tmp_reg
671671
|| break;
672672
|| case ZEND_DIV:
673-
| SSE_OP divsd, reg, addr
673+
| SSE_OP divsd, reg, addr, tmp_reg
674674
|| break;
675675
|| }
676676
|.endmacro
@@ -703,9 +703,9 @@ static void* dasm_labels[zend_lb_MAX];
703703
|| }
704704
|.endmacro
705705

706-
|.macro AVX_OP, avx_ins, reg, op1_reg, addr
706+
|.macro AVX_OP, avx_ins, reg, op1_reg, addr, tmp_reg
707707
|| if (Z_MODE(addr) == IS_CONST_ZVAL) {
708-
| MEM_OP3_3 avx_ins, xmm(reg-ZREG_XMM0), xmm(op1_reg-ZREG_XMM0), qword, Z_ZV(addr), r0
708+
| MEM_OP3_3 avx_ins, xmm(reg-ZREG_XMM0), xmm(op1_reg-ZREG_XMM0), qword, Z_ZV(addr), tmp_reg
709709
|| } else if (Z_MODE(addr) == IS_MEM_ZVAL) {
710710
| avx_ins xmm(reg-ZREG_XMM0), xmm(op1_reg-ZREG_XMM0), qword [Ra(Z_REG(addr))+Z_OFFSET(addr)]
711711
|| } else if (Z_MODE(addr) == IS_REG) {
@@ -715,19 +715,19 @@ static void* dasm_labels[zend_lb_MAX];
715715
|| }
716716
|.endmacro
717717

718-
|.macro AVX_MATH, opcode, reg, op1_reg, addr
718+
|.macro AVX_MATH, opcode, reg, op1_reg, addr, tmp_reg
719719
|| switch (opcode) {
720720
|| case ZEND_ADD:
721-
| AVX_OP vaddsd, reg, op1_reg, addr
721+
| AVX_OP vaddsd, reg, op1_reg, addr, tmp_reg
722722
|| break;
723723
|| case ZEND_SUB:
724-
| AVX_OP vsubsd, reg, op1_reg, addr
724+
| AVX_OP vsubsd, reg, op1_reg, addr, tmp_reg
725725
|| break;
726726
|| case ZEND_MUL:
727-
| AVX_OP vmulsd, reg, op1_reg, addr
727+
| AVX_OP vmulsd, reg, op1_reg, addr, tmp_reg
728728
|| break;
729729
|| case ZEND_DIV:
730-
| AVX_OP vdivsd, reg, op1_reg, addr
730+
| AVX_OP vdivsd, reg, op1_reg, addr, tmp_reg
731731
|| break;
732732
|| }
733733
|.endmacro
@@ -4323,10 +4323,20 @@ static int zend_jit_math_long_double(dasm_State **Dst,
43234323
(Z_MODE(res_addr) == IS_REG) ? Z_REG(res_addr) : ZREG_XMM0;
43244324

43254325
| SSE_GET_ZVAL_LVAL result_reg, op1_addr
4326-
if (JIT_G(opt_flags) & allowed_opt_flags & ZEND_JIT_CPU_AVX) {
4327-
| AVX_MATH opcode, result_reg, result_reg, op2_addr
4326+
4327+
if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_R0) {
4328+
/* ASSIGN_DIM_OP */
4329+
if (JIT_G(opt_flags) & allowed_opt_flags & ZEND_JIT_CPU_AVX) {
4330+
| AVX_MATH opcode, result_reg, result_reg, op2_addr, r1
4331+
} else {
4332+
| SSE_MATH opcode, result_reg, op2_addr, r1
4333+
}
43284334
} else {
4329-
| SSE_MATH opcode, result_reg, op2_addr
4335+
if (JIT_G(opt_flags) & allowed_opt_flags & ZEND_JIT_CPU_AVX) {
4336+
| AVX_MATH opcode, result_reg, result_reg, op2_addr, r0
4337+
} else {
4338+
| SSE_MATH opcode, result_reg, op2_addr, r0
4339+
}
43304340
}
43314341
| SSE_SET_ZVAL_DVAL res_addr, result_reg
43324342

@@ -4356,10 +4366,19 @@ static int zend_jit_math_double_long(dasm_State **Dst,
43564366
result_reg = ZREG_XMM0;
43574367
}
43584368
| SSE_GET_ZVAL_LVAL result_reg, op2_addr
4359-
if (JIT_G(opt_flags) & allowed_opt_flags & ZEND_JIT_CPU_AVX) {
4360-
| AVX_MATH opcode, result_reg, result_reg, op1_addr
4369+
if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_R0) {
4370+
/* ASSIGN_DIM_OP */
4371+
if (JIT_G(opt_flags) & allowed_opt_flags & ZEND_JIT_CPU_AVX) {
4372+
| AVX_MATH opcode, result_reg, result_reg, op1_addr, r1
4373+
} else {
4374+
| SSE_MATH opcode, result_reg, op1_addr, r1
4375+
}
43614376
} else {
4362-
| SSE_MATH opcode, result_reg, op1_addr
4377+
if (JIT_G(opt_flags) & allowed_opt_flags & ZEND_JIT_CPU_AVX) {
4378+
| AVX_MATH opcode, result_reg, result_reg, op1_addr, r0
4379+
} else {
4380+
| SSE_MATH opcode, result_reg, op1_addr, r0
4381+
}
43634382
}
43644383
} else {
43654384
zend_reg tmp_reg;
@@ -4454,8 +4473,11 @@ static int zend_jit_math_double_double(dasm_State **Dst,
44544473
if ((opcode == ZEND_MUL) &&
44554474
Z_MODE(val_addr) == IS_CONST_ZVAL && Z_DVAL_P(Z_ZV(val_addr)) == 2.0) {
44564475
| AVX_MATH_REG ZEND_ADD, result_reg, op1_reg, op1_reg
4476+
} else if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_R0) {
4477+
/* ASSIGN_DIM_OP */
4478+
| AVX_MATH opcode, result_reg, op1_reg, val_addr, r1
44574479
} else {
4458-
| AVX_MATH opcode, result_reg, op1_reg, val_addr
4480+
| AVX_MATH opcode, result_reg, op1_reg, val_addr, r0
44594481
}
44604482
} else {
44614483
zend_jit_addr val_addr;
@@ -4472,8 +4494,11 @@ static int zend_jit_math_double_double(dasm_State **Dst,
44724494
} else if ((opcode == ZEND_MUL) &&
44734495
Z_MODE(val_addr) == IS_CONST_ZVAL && Z_DVAL_P(Z_ZV(val_addr)) == 2.0) {
44744496
| SSE_MATH_REG ZEND_ADD, result_reg, result_reg
4497+
} else if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_R0) {
4498+
/* ASSIGN_DIM_OP */
4499+
| SSE_MATH opcode, result_reg, val_addr, r1
44754500
} else {
4476-
| SSE_MATH opcode, result_reg, val_addr
4501+
| SSE_MATH opcode, result_reg, val_addr, r0
44774502
}
44784503
}
44794504
| SSE_SET_ZVAL_DVAL res_addr, result_reg

0 commit comments

Comments
 (0)