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Sainath Grandhiwenlingz
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hv: Shuffle logic in vlapic_set_apicbase API implementation
This patch changes the code in vlapic_set_apicbase for the following reasons 1) Better readability as it first checks if the new value programmed into MSR is any different from the existing value cached in guest structures 2) Check if both bits 11:10 are set before enabling x2APIC mode for guest. Current code does not check if Bit 11 is set. 3) Add TODO in the comments, to detail about the current gaps in IA32_APIC_BASE MSR emulation. Tracked-On: #3253 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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hypervisor/arch/x86/guest/vlapic.c

Lines changed: 34 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -54,9 +54,10 @@ static inline uint32_t prio(uint32_t x)
5454
}
5555

5656
#define VLAPIC_VERSION (16U)
57-
5857
#define APICBASE_BSP 0x00000100UL
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#define APICBASE_X2APIC 0x00000400U
59+
#define APICBASE_XAPIC 0x00000800U
60+
#define APICBASE_LAPIC_MODE (APICBASE_XAPIC | APICBASE_X2APIC)
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#define APICBASE_ENABLED 0x00000800UL
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#define LOGICAL_ID_MASK 0xFU
6263
#define CLUSTER_ID_MASK 0xFFFF0U
@@ -1763,20 +1764,39 @@ int32_t vlapic_set_apicbase(struct acrn_vlapic *vlapic, uint64_t new)
17631764
{
17641765
int32_t ret = 0;
17651766
uint64_t changed;
1766-
changed = vlapic->msr_apicbase ^ new;
1767+
bool change_in_vlapic_mode = false;
17671768

1768-
if ((changed == APICBASE_X2APIC) && ((new & APICBASE_X2APIC) == APICBASE_X2APIC)) {
1769-
atomic_set64(&vlapic->msr_apicbase, changed);
1770-
vlapic_build_x2apic_id(vlapic);
1771-
switch_apicv_mode_x2apic(vlapic->vcpu);
1772-
ret = 0;
1773-
} else if (vlapic->msr_apicbase != new) {
1774-
dev_dbg(ACRN_DBG_LAPIC,
1775-
"NOT support to change APIC_BASE MSR from %#lx to %#lx",
1776-
vlapic->msr_apicbase, new);
1777-
ret = -1;
1778-
} else {
1779-
/* No other state currently, do nothing */
1769+
1770+
if (vlapic->msr_apicbase != new) {
1771+
changed = vlapic->msr_apicbase ^ new;
1772+
change_in_vlapic_mode = ((changed & APICBASE_LAPIC_MODE) != 0U);
1773+
1774+
/*
1775+
* TODO: Logic to check for change in Reserved Bits and Inject GP
1776+
*/
1777+
1778+
1779+
/*
1780+
* Logic to check for change in Bits 11:10 for vLAPIC mode switch
1781+
*/
1782+
if (change_in_vlapic_mode) {
1783+
if ((new & APICBASE_LAPIC_MODE) ==
1784+
(APICBASE_XAPIC | APICBASE_X2APIC)) {
1785+
vlapic->msr_apicbase = new;
1786+
vlapic_build_x2apic_id(vlapic);
1787+
switch_apicv_mode_x2apic(vlapic->vcpu);
1788+
} else {
1789+
/*
1790+
* TODO: Logic to check for Invalid transitions, Invalid State
1791+
* and mode switch according to SDM 10.12.5
1792+
* Fig. 10-27
1793+
*/
1794+
}
1795+
}
1796+
1797+
/*
1798+
* TODO: Logic to check for change in Bits 35:12 and Bit 7 and emulate
1799+
*/
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}
17811801

17821802
return ret;

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