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HV: Adding passthru vdev device support for partition hypervisor
V4: - Renamed members for struct pcibar and changed code accordingly V3: - Do not use ASSERT - Use EPT_XX defines when claling ept_mr_add - Report 64-bit MMIO physical bar to UOS as 32-bit virtual bar (assume bar size is always less than 4GB), which removed quite some of 64-bit bar handling code Reviewed-by: Anthony Xu <anthony.xu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com> Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
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4 files changed

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lines changed

‎hypervisor/dm/vpci/pci_priv.h

Lines changed: 72 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,4 +78,76 @@
7878
void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, uint16_t vbdf,
7979
uint32_t offset, uint32_t bytes, uint32_t *val);
8080

81+
static inline uint8_t
82+
pci_vdev_read_cfg_u8(struct pci_vdev *vdev, uint32_t offset)
83+
{
84+
return (*(uint8_t *)(&vdev->cfgdata[0] + offset));
85+
}
86+
87+
static inline uint16_t pci_vdev_read_cfg_u16(struct pci_vdev *vdev,
88+
uint32_t offset)
89+
{
90+
return (*(uint16_t *)(&vdev->cfgdata[0] + offset));
91+
}
92+
93+
static inline uint32_t pci_vdev_read_cfg_u32(struct pci_vdev *vdev,
94+
uint32_t offset)
95+
{
96+
return (*(uint32_t *)(&vdev->cfgdata[0] + offset));
97+
}
98+
99+
static inline void
100+
pci_vdev_write_cfg_u8(struct pci_vdev *vdev, uint32_t offset, uint8_t val)
101+
{
102+
*(uint8_t *)(vdev->cfgdata + offset) = val;
103+
}
104+
105+
static inline void
106+
pci_vdev_write_cfg_u16(struct pci_vdev *vdev, uint32_t offset, uint16_t val)
107+
{
108+
*(uint16_t *)(vdev->cfgdata + offset) = val;
109+
}
110+
111+
static inline void
112+
pci_vdev_write_cfg_u32(struct pci_vdev *vdev, uint32_t offset, uint32_t val)
113+
{
114+
*(uint32_t *)(vdev->cfgdata + offset) = val;
115+
}
116+
117+
static inline uint32_t pci_vdev_read_cfg(struct pci_vdev *vdev,
118+
uint32_t offset, uint32_t bytes)
119+
{
120+
uint32_t val;
121+
122+
switch (bytes) {
123+
case 1U:
124+
val = pci_vdev_read_cfg_u8(vdev, offset);
125+
break;
126+
case 2U:
127+
val = pci_vdev_read_cfg_u16(vdev, offset);
128+
break;
129+
default:
130+
val = pci_vdev_read_cfg_u32(vdev, offset);
131+
break;
132+
}
133+
134+
return val;
135+
}
136+
137+
static inline void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset,
138+
uint32_t bytes, uint32_t val)
139+
{
140+
switch (bytes) {
141+
case 1U:
142+
pci_vdev_write_cfg_u8(vdev, offset, val);
143+
break;
144+
case 2U:
145+
pci_vdev_write_cfg_u16(vdev, offset, val);
146+
break;
147+
default:
148+
pci_vdev_write_cfg_u32(vdev, offset, val);
149+
break;
150+
}
151+
}
152+
81153
#endif /* PCI_PRIV_H_ */

‎hypervisor/dm/vpci/pci_pt.c

Lines changed: 292 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,292 @@
1+
/*-
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* Copyright (c) 2011 NetApp, Inc.
3+
* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
7+
* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
13+
* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20+
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21+
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22+
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23+
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25+
* SUCH DAMAGE.
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*
27+
* $FreeBSD$
28+
*/
29+
30+
/* Passthrough PCI device related operations */
31+
32+
#include <hypervisor.h>
33+
#include <hv_lib.h>
34+
#include <acrn_common.h>
35+
#include <hv_arch.h>
36+
#include <hv_debug.h>
37+
#include "pci_priv.h"
38+
39+
40+
static spinlock_t pci_device_lock = { .head = 0, .tail = 0 };
41+
42+
43+
static uint32_t pci_pdev_calc_address(uint16_t bdf, uint32_t offset)
44+
{
45+
uint32_t addr = bdf;
46+
47+
addr <<= 8;
48+
addr |= (offset | PCI_CFG_ENABLE);
49+
50+
return addr;
51+
}
52+
53+
static uint32_t pci_pdev_read_cfg(struct pci_pdev *pdev,
54+
uint32_t offset, uint32_t bytes)
55+
{
56+
uint32_t addr;
57+
uint32_t val;
58+
59+
spinlock_obtain(&pci_device_lock);
60+
61+
addr = pci_pdev_calc_address(pdev->bdf, offset);
62+
63+
/* Write address to ADDRESS register */
64+
pio_write(addr, PCI_CONFIG_ADDR, 4);
65+
66+
/* Read result from DATA register */
67+
switch (bytes) {
68+
case 1U:
69+
val = pio_read8(PCI_CONFIG_DATA + (offset & 3U));
70+
break;
71+
case 2U:
72+
val = pio_read16(PCI_CONFIG_DATA + (offset & 2U));
73+
break;
74+
default:
75+
val = pio_read32(PCI_CONFIG_DATA);
76+
break;
77+
}
78+
spinlock_release(&pci_device_lock);
79+
80+
return val;
81+
}
82+
83+
static void pci_pdev_write_cfg(struct pci_pdev *pdev, uint32_t offset,
84+
uint32_t bytes, uint32_t val)
85+
{
86+
uint32_t addr;
87+
88+
spinlock_obtain(&pci_device_lock);
89+
90+
addr = pci_pdev_calc_address(pdev->bdf, offset);
91+
92+
/* Write address to ADDRESS register */
93+
pio_write(addr, PCI_CONFIG_ADDR, 4);
94+
95+
/* Write value to DATA register */
96+
switch (bytes) {
97+
case 1U:
98+
pio_write8(val, PCI_CONFIG_DATA + (offset & 3U));
99+
break;
100+
case 2U:
101+
pio_write16(val, PCI_CONFIG_DATA + (offset & 2U));
102+
break;
103+
default:
104+
pio_write32(val, PCI_CONFIG_DATA);
105+
break;
106+
}
107+
spinlock_release(&pci_device_lock);
108+
}
109+
110+
static int vdev_pt_init_validate(struct pci_vdev *vdev)
111+
{
112+
uint32_t idx;
113+
114+
for (idx = 0; idx < (uint32_t)PCI_BAR_COUNT; idx++) {
115+
if (vdev->bar[idx].type != PCIM_BAR_MEM_32) {
116+
return -EINVAL;
117+
}
118+
}
119+
120+
return 0;
121+
}
122+
123+
static void vdev_pt_init_bar_registers(struct pci_vdev *vdev)
124+
{
125+
uint32_t idx;
126+
127+
for (idx = 0; idx < (uint32_t)PCI_BAR_COUNT; idx++) {
128+
/* Initialize the BAR register in config space */
129+
pci_vdev_write_cfg_u32(vdev, PCIR_BAR(idx),
130+
PCI_BAR(vdev->bar[idx].base, vdev->bar[idx].type));
131+
}
132+
}
133+
134+
static int vdev_pt_init(struct pci_vdev *vdev)
135+
{
136+
int ret;
137+
struct vm *vm = vdev->vpci->vm;
138+
139+
ret = vdev_pt_init_validate(vdev);
140+
if (ret != 0) {
141+
pr_err("virtual bar can only be of type PCIM_BAR_MEM_32!");
142+
return ret;
143+
}
144+
145+
/* Create an iommu domain for target VM if not created */
146+
if (vm->iommu == NULL) {
147+
if (vm->arch_vm.nworld_eptp == 0UL) {
148+
vm->arch_vm.nworld_eptp = alloc_paging_struct();
149+
}
150+
vm->iommu = create_iommu_domain(vm->vm_id,
151+
HVA2HPA(vm->arch_vm.nworld_eptp), 48U);
152+
}
153+
154+
ret = assign_iommu_device(vm->iommu,
155+
PCI_BUS(vdev->pdev.bdf), LOBYTE(vdev->pdev.bdf));
156+
157+
vdev_pt_init_bar_registers(vdev);
158+
159+
return ret;
160+
}
161+
162+
static int vdev_pt_deinit(struct pci_vdev *vdev)
163+
{
164+
int ret;
165+
struct vm *vm = vdev->vpci->vm;
166+
167+
ret = unassign_iommu_device(vm->iommu, PCI_BUS(vdev->pdev.bdf),
168+
LOBYTE(vdev->pdev.bdf));
169+
170+
return ret;
171+
}
172+
173+
static int bar_access(uint32_t coff)
174+
{
175+
if ((coff >= PCIR_BAR(0U)) && (coff < PCIR_BAR(PCI_BAR_COUNT))) {
176+
return 1;
177+
} else {
178+
return 0;
179+
}
180+
}
181+
182+
static int vdev_pt_cfgread(struct pci_vdev *vdev, uint32_t offset,
183+
uint32_t bytes, uint32_t *val)
184+
{
185+
/* Assumption: access needed to be aligned on 1/2/4 bytes */
186+
if ((offset & (bytes - 1)) != 0U) {
187+
*val = 0xffffffffU;
188+
return -EINVAL;
189+
}
190+
191+
/* PCI BARs is emulated */
192+
if (bar_access(offset)) {
193+
*val = pci_vdev_read_cfg(vdev, offset, bytes);
194+
} else {
195+
*val = pci_pdev_read_cfg(&vdev->pdev, offset, bytes);
196+
}
197+
198+
return 0;
199+
}
200+
201+
static int vdev_pt_remap_bar(struct pci_vdev *vdev, uint32_t idx,
202+
uint32_t new_base)
203+
{
204+
int error = 0;
205+
struct vm *vm = vdev->vpci->vm;
206+
207+
if (vdev->bar[idx].base != 0) {
208+
error = ept_mr_del(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
209+
vdev->bar[idx].base,
210+
vdev->bar[idx].size);
211+
if (error) {
212+
return error;
213+
}
214+
}
215+
216+
if (new_base != 0U) {
217+
/* Map the physical BAR in the guest MMIO space */
218+
error = ept_mr_add(vm,
219+
vdev->pdev.bar[idx].base, /* HPA */
220+
new_base, /*GPA*/
221+
vdev->bar[idx].size,
222+
EPT_WR | EPT_RD | EPT_UNCACHED);
223+
if (error) {
224+
return error;
225+
}
226+
}
227+
return error;
228+
}
229+
230+
static uint32_t memen(struct pci_vdev *vdev)
231+
{
232+
return pci_pdev_read_cfg(&vdev->pdev, PCIR_COMMAND, 2)
233+
& PCIM_CMD_MEMEN;
234+
}
235+
236+
static void vdev_pt_cfgwrite_bar(struct pci_vdev *vdev, uint32_t offset,
237+
uint32_t bytes, uint32_t new_bar_uos)
238+
{
239+
uint32_t idx;
240+
uint32_t new_bar, mask;
241+
bool bar_update_normal = 1;
242+
bool do_map;
243+
int error;
244+
245+
idx = (offset - PCIR_BAR(0U)) / 4U;
246+
mask = ~(vdev->bar[idx].size - 1U);
247+
bar_update_normal = (new_bar_uos != (uint32_t)~0U);
248+
new_bar = new_bar_uos & mask;
249+
new_bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
250+
251+
if (PCI_BAR_BASE(new_bar) == vdev->bar[idx].base) {
252+
return;
253+
}
254+
255+
do_map = (memen(vdev)) && bar_update_normal;
256+
if (do_map) {
257+
error = vdev_pt_remap_bar(vdev, idx, PCI_BAR_BASE(new_bar));
258+
if (error) {
259+
pr_err("vdev_pt_remap_bar failed: %d", idx);
260+
}
261+
}
262+
263+
pci_vdev_write_cfg_u32(vdev, offset, new_bar);
264+
vdev->bar[idx].base = PCI_BAR_BASE(new_bar);
265+
}
266+
267+
static int vdev_pt_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
268+
uint32_t bytes, uint32_t val)
269+
{
270+
/* Assumption: access needed to be aligned on 1/2/4 bytes */
271+
if ((offset & (bytes - 1)) != 0U) {
272+
return -EINVAL;
273+
}
274+
275+
/* PCI BARs are emulated */
276+
if (bar_access(offset)) {
277+
vdev_pt_cfgwrite_bar(vdev, offset, bytes, val);
278+
} else {
279+
/* Write directly to physical device's config space */
280+
pci_pdev_write_cfg(&vdev->pdev, offset, bytes, val);
281+
}
282+
283+
return 0;
284+
}
285+
286+
struct pci_vdev_ops pci_ops_vdev_pt = {
287+
.init = vdev_pt_init,
288+
.deinit = vdev_pt_deinit,
289+
.cfgwrite = vdev_pt_cfgwrite,
290+
.cfgread = vdev_pt_cfgread,
291+
};
292+

‎hypervisor/include/dm/vpci/vpci.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,8 @@ struct vpci {
9292
struct pci_addr_info addr_info;
9393
};
9494

95+
extern struct pci_vdev_ops pci_ops_vdev_pt;
96+
9597
void vpci_init(struct vm *vm);
9698
void vpci_cleanup(struct vm *vm);
9799

‎hypervisor/partition/vm_description.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ static struct vpci_vdev_array vpci_vdev_array1 = {
1919

2020
{/*vdev 1*/
2121
.vbdf = PCI_BDF(0x00U, 0x01U, 0x00U),
22-
.ops = NULL,
22+
.ops = &pci_ops_vdev_pt,
2323
.bar = {
2424
[0] = {
2525
.base = 0UL,
@@ -65,7 +65,7 @@ static struct vpci_vdev_array vpci_vdev_array2 = {
6565

6666
{/*vdev 1*/
6767
.vbdf = PCI_BDF(0x00U, 0x01U, 0x00U),
68-
.ops = NULL,
68+
.ops = &pci_ops_vdev_pt,
6969
.bar = {
7070
[0] = {
7171
.base = 0UL,

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