Skip to content

Commit 183ca5d

Browse files
donshenglijinxia
donsheng
authored and
lijinxia
committed
HV: Adding hostbridge vdev device support for partition hypervisor
V4: - Moved error checking to vdev_hostbridge_cfgwrite/vdev_hostbridge_cfgread V3: - Unified ops calling and implemented deinit/cfgwrite/cfgread ops, previously only init op is implemented Reviewed-by: Anthony Xu <anthony.xu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com> Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
1 parent 181de19 commit 183ca5d

File tree

3 files changed

+132
-2
lines changed

3 files changed

+132
-2
lines changed

‎hypervisor/dm/vpci/hostbridge.c

Lines changed: 129 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,129 @@
1+
/*-
2+
* Copyright (c) 2011 NetApp, Inc.
3+
* Copyright (c) 2018 Intel Corporation
4+
* All rights reserved.
5+
*
6+
* Redistribution and use in source and binary forms, with or without
7+
* modification, are permitted provided that the following conditions
8+
* are met:
9+
* 1. Redistributions of source code must retain the above copyright
10+
* notice, this list of conditions and the following disclaimer.
11+
* 2. Redistributions in binary form must reproduce the above copyright
12+
* notice, this list of conditions and the following disclaimer in the
13+
* documentation and/or other materials provided with the distribution.
14+
*
15+
* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
16+
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17+
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18+
* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
19+
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20+
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21+
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22+
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23+
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24+
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25+
* SUCH DAMAGE.
26+
*
27+
* $FreeBSD$
28+
*/
29+
30+
31+
/*_
32+
* Emulate a PCI Host bridge:
33+
* Intel Corporation Celeron N3350/Pentium N4200/Atom E3900
34+
* Series Host Bridge (rev 0b)
35+
*/
36+
37+
#include <hypervisor.h>
38+
#include <hv_lib.h>
39+
#include <acrn_common.h>
40+
#include <hv_arch.h>
41+
#include <hv_debug.h>
42+
#include "pci_priv.h"
43+
44+
static int vdev_hostbridge_init(struct pci_vdev *vdev)
45+
{
46+
/* PCI config space */
47+
pci_vdev_write_cfg_u16(vdev, PCIR_VENDOR, 0x8086U);
48+
pci_vdev_write_cfg_u16(vdev, PCIR_DEVICE, 0x5af0U);
49+
50+
pci_vdev_write_cfg_u8(vdev, PCIR_REVID, 0xbU);
51+
52+
pci_vdev_write_cfg_u8(vdev, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL
53+
| PCIM_MFDEV);
54+
pci_vdev_write_cfg_u8(vdev, PCIR_CLASS, PCIC_BRIDGE);
55+
pci_vdev_write_cfg_u8(vdev, PCIR_SUBCLASS, PCIS_BRIDGE_HOST);
56+
57+
pci_vdev_write_cfg_u8(vdev, 0x34U, 0xe0U);
58+
pci_vdev_write_cfg_u8(vdev, 0x3cU, 0xe0U);
59+
pci_vdev_write_cfg_u8(vdev, 0x48U, 0x1U);
60+
pci_vdev_write_cfg_u8(vdev, 0x4aU, 0xd1U);
61+
pci_vdev_write_cfg_u8(vdev, 0x4bU, 0xfeU);
62+
pci_vdev_write_cfg_u8(vdev, 0x50U, 0xc1U);
63+
pci_vdev_write_cfg_u8(vdev, 0x51U, 0x2U);
64+
pci_vdev_write_cfg_u8(vdev, 0x54U, 0x33U);
65+
pci_vdev_write_cfg_u8(vdev, 0x58U, 0x7U);
66+
pci_vdev_write_cfg_u8(vdev, 0x5aU, 0xf0U);
67+
pci_vdev_write_cfg_u8(vdev, 0x5bU, 0x7fU);
68+
pci_vdev_write_cfg_u8(vdev, 0x60U, 0x1U);
69+
pci_vdev_write_cfg_u8(vdev, 0x63U, 0xe0U);
70+
pci_vdev_write_cfg_u8(vdev, 0xabU, 0x80U);
71+
pci_vdev_write_cfg_u8(vdev, 0xacU, 0x2U);
72+
pci_vdev_write_cfg_u8(vdev, 0xb0U, 0x1U);
73+
pci_vdev_write_cfg_u8(vdev, 0xb3U, 0x7cU);
74+
pci_vdev_write_cfg_u8(vdev, 0xb4U, 0x1U);
75+
pci_vdev_write_cfg_u8(vdev, 0xb6U, 0x80U);
76+
pci_vdev_write_cfg_u8(vdev, 0xb7U, 0x7bU);
77+
pci_vdev_write_cfg_u8(vdev, 0xb8U, 0x1U);
78+
pci_vdev_write_cfg_u8(vdev, 0xbbU, 0x7bU);
79+
pci_vdev_write_cfg_u8(vdev, 0xbcU, 0x1U);
80+
pci_vdev_write_cfg_u8(vdev, 0xbfU, 0x80U);
81+
pci_vdev_write_cfg_u8(vdev, 0xe0U, 0x9U);
82+
pci_vdev_write_cfg_u8(vdev, 0xe2U, 0xcU);
83+
pci_vdev_write_cfg_u8(vdev, 0xe3U, 0x1U);
84+
pci_vdev_write_cfg_u8(vdev, 0xf5U, 0xfU);
85+
pci_vdev_write_cfg_u8(vdev, 0xf6U, 0x1cU);
86+
pci_vdev_write_cfg_u8(vdev, 0xf7U, 0x1U);
87+
88+
return 0;
89+
}
90+
91+
static int vdev_hostbridge_deinit(__unused struct pci_vdev *vdev)
92+
{
93+
return 0;
94+
}
95+
96+
static int vdev_hostbridge_cfgread(struct pci_vdev *vdev, uint32_t offset,
97+
uint32_t bytes, uint32_t *val)
98+
{
99+
/* Assumption: access needed to be aligned on 1/2/4 bytes */
100+
if ((offset & (bytes - 1)) != 0U) {
101+
*val = 0xffffffffU;
102+
return -EINVAL;
103+
}
104+
105+
*val = pci_vdev_read_cfg(vdev, offset, bytes);
106+
107+
return 0;
108+
}
109+
110+
static int vdev_hostbridge_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
111+
uint32_t bytes, uint32_t val)
112+
{
113+
/* Assumption: access needed to be aligned on 1/2/4 bytes */
114+
if ((offset & (bytes - 1)) != 0U) {
115+
return -EINVAL;
116+
}
117+
118+
pci_vdev_write_cfg(vdev, offset, bytes, val);
119+
120+
return 0;
121+
}
122+
123+
struct pci_vdev_ops pci_ops_vdev_hostbridge = {
124+
.init = vdev_hostbridge_init,
125+
.deinit = vdev_hostbridge_deinit,
126+
.cfgwrite = vdev_hostbridge_cfgwrite,
127+
.cfgread = vdev_hostbridge_cfgread,
128+
};
129+

‎hypervisor/include/dm/vpci/vpci.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,7 @@ struct vpci {
9292
struct pci_addr_info addr_info;
9393
};
9494

95+
extern struct pci_vdev_ops pci_ops_vdev_hostbridge;
9596
extern struct pci_vdev_ops pci_ops_vdev_pt;
9697

9798
void vpci_init(struct vm *vm);

‎hypervisor/partition/vm_description.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ static struct vpci_vdev_array vpci_vdev_array1 = {
1212
.vpci_vdev_list = {
1313
{/*vdev 0: hostbridge */
1414
.vbdf = PCI_BDF(0x00U, 0x00U, 0x00U),
15-
.ops = NULL,
15+
.ops = &pci_ops_vdev_hostbridge,
1616
.bar = {}, /* don't care for hostbridge */
1717
.pdev = {} /* don't care for hostbridge */
1818
},
@@ -58,7 +58,7 @@ static struct vpci_vdev_array vpci_vdev_array2 = {
5858
.vpci_vdev_list = {
5959
{/*vdev 0: hostbridge*/
6060
.vbdf = PCI_BDF(0x00U, 0x00U, 0x00U),
61-
.ops = NULL,
61+
.ops = &pci_ops_vdev_hostbridge,
6262
.bar = {}, /* don't care for hostbridge */
6363
.pdev = {} /* don't care for hostbridge */
6464
},

0 commit comments

Comments
 (0)