hv: add function to check if using posted interrupt is possible for vm

Add platform_caps.c to maintain platform related information

Set platform_caps.pi to true if all iommus are posted interrupt capable, false
otherwise

If lapic passthru is not configured and platform_caps.pi is true, the vm
may be able to use posted interrupt for a ptdev, if the ptdev's IRQ is
single-destination

Tracked-On: #4506
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@Intel.com>

Author: donsheng

hypervisor/Makefile

@@ -229,6 +229,7 @@ HW_C_SRCS += arch/x86/ioapic.c
 HW_C_SRCS += arch/x86/lapic.c
 HW_C_SRCS += arch/x86/cpu.c
 HW_C_SRCS += arch/x86/cpu_caps.c
+HW_C_SRCS += arch/x86/platform_caps.c
 HW_C_SRCS += arch/x86/security.c
 HW_C_SRCS += arch/x86/mmu.c
 HW_C_SRCS += arch/x86/e820.c

hypervisor/arch/x86/guest/vm.c

@@ -31,6 +31,7 @@
 #include <sbuf.h>
 #include <pci_dev.h>
 #include <vacpi.h>
+#include <platform_caps.h>
 
 vm_sw_loader_t vm_sw_loader;
 
@@ -115,6 +116,20 @@ bool is_rt_vm(const struct acrn_vm *vm)
 	return ((vm_config->guest_flags & GUEST_FLAG_RT) != 0U);
 }
 
+/**
+ * @brief VT-d PI posted mode can possibly be used for PTDEVs assigned
+ * to this VM if platform supports VT-d PI AND lapic passthru is not configured
+ * for this VM.
+ * However, as we can only post single destination IRQ, so meeting these 2 conditions
+ * does not necessarily mean posted mode will be used for all PTDEVs belonging
+ * to the VM, unless the IRQ is single-destination for the specific PTDEV
+ * @pre vm != NULL
+ */
+bool is_pi_capable(const struct acrn_vm *vm)
+{
+	return (platform_caps.pi && (!is_lapic_pt_configured(vm)));
+}
+
 static struct acrn_vm *get_highest_severity_vm(void)
 {
 	uint16_t vm_id, highest_vm_id = 0U;

hypervisor/arch/x86/platform_caps.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <types.h>
+#include <platform_caps.h>
+
+struct platform_caps_x86 platform_caps = {.pi = true};

hypervisor/arch/x86/vtd.c

@@ -23,6 +23,7 @@
 #include <vm_config.h>
 #include <pci.h>
 #include <vm.h>
+#include <platform_caps.h>
 
 #define DBG_IOMMU 0
 
@@ -208,6 +209,7 @@ static inline uint16_t vmid_to_domainid(uint16_t vm_id)
 
 static int32_t dmar_register_hrhd(struct dmar_drhd_rt *dmar_unit);
 static struct dmar_drhd_rt *device_to_dmaru(uint8_t bus, uint8_t devfun);
+
 static int32_t register_hrhd_units(void)
 {
 	struct dmar_drhd_rt *drhd_rt;
@@ -226,6 +228,10 @@ static int32_t register_hrhd_units(void)
 		if (ret != 0) {
 			break;
 		}
+
+		if ((iommu_cap_pi(drhd_rt->cap) == 0U) || (!is_apicv_advanced_feature_supported())) {
+			platform_caps.pi = false;
+		}
 	}
 
 	return ret;

hypervisor/include/arch/x86/guest/vm.h

@@ -263,6 +263,7 @@ void vrtc_init(struct acrn_vm *vm);
 
 bool is_lapic_pt_configured(const struct acrn_vm *vm);
 bool is_rt_vm(const struct acrn_vm *vm);
+bool is_pi_capable(const struct acrn_vm *vm);
 bool has_rt_vm(void);
 bool is_highest_severity_vm(const struct acrn_vm *vm);
 bool vm_hide_mtrr(const struct acrn_vm *vm);

hypervisor/include/arch/x86/platform_caps.h

@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_CAPS_H
+#define PLATFORM_CAPS_H
+
+struct platform_caps_x86 {
+	/* true if posted interrupt is supported by all IOMMUs */
+	bool pi;
+};
+
+extern struct platform_caps_x86 platform_caps;
+
+#endif /* PLATFORM_CAPS_H */