HV: add px data of bxt j3455 SOC

The cpu model name of "Intel(R) Celeron(R) CPU J3455 @ 1.50GHz" is used for
APL NUC which is in Acrn official suport list.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>

Author: jsun26intel

hypervisor/arch/x86/cpu_state_tbl.c

@@ -55,8 +55,22 @@ struct cpu_px_data px_a3960[] = {
 	{0x320, 0, 0xA, 0xA, 0x0800, 0x0800}  /* P16 */
 };
 
+/* The table includes cpu px info of Intel J3455 SoC */
+struct cpu_px_data px_j3455[] = {
+	{0x5DD, 0, 0xA, 0xA, 0x1700, 0x1700}, /* P0 */
+	{0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P1 */
+	{0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P2 */
+	{0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P3 */
+	{0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P4 */
+	{0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P5 */
+	{0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P6 */
+	{0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P7 */
+	{0x320, 0, 0xA, 0xA, 0x0800, 0x0800}  /* P8 */
+};
+
 struct cpu_state_table cpu_state_tbl[] = {
-	{"Intel(R) Atom(TM) Processor A3960 @ 1.90GHz", 17, px_a3960}
+	{"Intel(R) Atom(TM) Processor A3960 @ 1.90GHz", 17, px_a3960},
+	{"Intel(R) Celeron(R) CPU J3455 @ 1.50GHz", 9, px_j3455}
 };
 
 static int get_state_tbl_idx(char *cpuname)