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Wei Liuwenlingz
Wei Liu
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acrn-config: add config files for whl-ipc-i7 board
Add board/scenario/launch config files for whl-ipc-i7. Tracked-On: #3854 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
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‎misc/acrn-config/xmls/board-xmls/whl-ipc-i7.xml

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<acrn-config board="whl-ipc-i7">
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<BIOS_INFO>
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BIOS Information
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Vendor: American Megatrends Inc.
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Version: WL10R104
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Release Date: 09/12/2019
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BIOS Revision: 5.13
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</BIOS_INFO>
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<BASE_BOARD_INFO>
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Base Board Information
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Manufacturer: Maxtang
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Product Name: WL10
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Version: V1.0
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</BASE_BOARD_INFO>
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<PCI_DEVICE>
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00:00.0 Host bridge: Intel Corporation Device 3e34 (rev 0b)
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00:02.0 VGA compatible controller: Intel Corporation Device 3ea0
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Region 0: Memory at a0000000 (64-bit, non-prefetchable) [size=16M]
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Region 2: Memory at 90000000 (64-bit, prefetchable) [size=256M]
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00:12.0 Signal processing controller: Intel Corporation Device 9df9 (rev 30)
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Region 0: Memory at a141e000 (64-bit, non-prefetchable) [size=4K]
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00:14.0 USB controller: Intel Corporation Device 9ded (rev 30)
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Region 0: Memory at a1400000 (64-bit, non-prefetchable) [size=64K]
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00:14.2 RAM memory: Intel Corporation Device 9def (rev 30)
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Region 0: Memory at a1416000 (64-bit, non-prefetchable) [disabled] [size=8K]
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Region 2: Memory at a141d000 (64-bit, non-prefetchable) [disabled] [size=4K]
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00:16.0 Communication controller: Intel Corporation Device 9de0 (rev 30)
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Region 0: Memory at a141c000 (64-bit, non-prefetchable) [size=4K]
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00:17.0 SATA controller: Intel Corporation Device 9dd3 (rev 30)
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Region 0: Memory at a1414000 (32-bit, non-prefetchable) [size=8K]
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Region 1: Memory at a141b000 (32-bit, non-prefetchable) [size=256]
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Region 5: Memory at a141a000 (32-bit, non-prefetchable) [size=2K]
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00:1a.0 SD Host controller: Intel Corporation Device 9dc4 (rev 30)
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Region 0: Memory at a1419000 (64-bit, non-prefetchable) [size=4K]
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00:1c.0 PCI bridge: Intel Corporation Device 9db8 (rev f0)
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00:1c.4 PCI bridge: Intel Corporation Device 9dbc (rev f0)
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00:1d.0 PCI bridge: Intel Corporation Device 9db0 (rev f0)
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00:1d.1 PCI bridge: Intel Corporation Device 9db1 (rev f0)
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00:1f.0 ISA bridge: Intel Corporation Device 9d84 (rev 30)
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00:1f.3 Audio device: Intel Corporation Device 9dc8 (rev 30)
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Region 0: Memory at a1410000 (64-bit, non-prefetchable) [size=16K]
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Region 4: Memory at a1000000 (64-bit, non-prefetchable) [size=1M]
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00:1f.4 SMBus: Intel Corporation Device 9da3 (rev 30)
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Region 0: Memory at a1418000 (64-bit, non-prefetchable) [size=256]
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00:1f.5 Serial bus controller [0c80]: Intel Corporation Device 9da4 (rev 30)
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Region 0: Memory at fe010000 (32-bit, non-prefetchable) [size=4K]
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02:00.0 Non-Volatile memory controller: Silicon Motion, Inc. Device 2263 (rev 03)
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Region 0: Memory at a1300000 (64-bit, non-prefetchable) [size=16K]
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03:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03)
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Region 0: Memory at a1200000 (32-bit, non-prefetchable) [size=128K]
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Region 3: Memory at a1220000 (32-bit, non-prefetchable) [size=16K]
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04:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03)
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Region 0: Memory at a1100000 (32-bit, non-prefetchable) [size=128K]
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Region 3: Memory at a1120000 (32-bit, non-prefetchable) [size=16K]
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</PCI_DEVICE>
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<PCI_VID_PID>
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00:00.0 0600: 8086:3e34 (rev 0b)
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00:02.0 0300: 8086:3ea0
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00:12.0 1180: 8086:9df9 (rev 30)
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00:14.0 0c03: 8086:9ded (rev 30)
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00:14.2 0500: 8086:9def (rev 30)
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00:16.0 0780: 8086:9de0 (rev 30)
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00:17.0 0106: 8086:9dd3 (rev 30)
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00:1a.0 0805: 8086:9dc4 (rev 30)
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00:1c.0 0604: 8086:9db8 (rev f0)
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00:1c.4 0604: 8086:9dbc (rev f0)
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00:1d.0 0604: 8086:9db0 (rev f0)
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00:1d.1 0604: 8086:9db1 (rev f0)
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00:1f.0 0601: 8086:9d84 (rev 30)
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00:1f.3 0403: 8086:9dc8 (rev 30)
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00:1f.4 0c05: 8086:9da3 (rev 30)
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00:1f.5 0c80: 8086:9da4 (rev 30)
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02:00.0 0108: 126f:2263 (rev 03)
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03:00.0 0200: 8086:157b (rev 03)
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04:00.0 0200: 8086:157b (rev 03)
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</PCI_VID_PID>
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<WAKE_VECTOR_INFO>
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#define WAKE_VECTOR_32 0x8C8AA08CUL
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#define WAKE_VECTOR_64 0x8C8AA098UL
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</WAKE_VECTOR_INFO>
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<RESET_REGISTER_INFO>
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#define RESET_REGISTER_ADDRESS 0xCF9UL
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#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
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#define RESET_REGISTER_VALUE 0x6U
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</RESET_REGISTER_INFO>
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<PM_INFO>
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#define PM1A_EVT_SPACE_ID SPACE_SYSTEM_IO
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#define PM1A_EVT_BIT_WIDTH 0x20U
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#define PM1A_EVT_BIT_OFFSET 0x0U
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#define PM1A_EVT_ADDRESS 0x1800UL
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#define PM1A_EVT_ACCESS_SIZE 0x2U
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#define PM1B_EVT_SPACE_ID SPACE_SYSTEM_IO
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#define PM1B_EVT_BIT_WIDTH 0x0U
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#define PM1B_EVT_BIT_OFFSET 0x0U
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#define PM1B_EVT_ADDRESS 0x0UL
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#define PM1B_EVT_ACCESS_SIZE 0x2U
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#define PM1A_CNT_SPACE_ID SPACE_SYSTEM_IO
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#define PM1A_CNT_BIT_WIDTH 0x10U
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#define PM1A_CNT_BIT_OFFSET 0x0U
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#define PM1A_CNT_ADDRESS 0x1804UL
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#define PM1A_CNT_ACCESS_SIZE 0x2U
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#define PM1B_CNT_SPACE_ID SPACE_SYSTEM_IO
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#define PM1B_CNT_BIT_WIDTH 0x0U
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#define PM1B_CNT_BIT_OFFSET 0x0U
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#define PM1B_CNT_ADDRESS 0x0UL
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#define PM1B_CNT_ACCESS_SIZE 0x2U
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</PM_INFO>
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<S3_INFO>
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/* S3 is not supported by BIOS */
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#define S3_PKG_VAL_PM1A 0x0U
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#define S3_PKG_VAL_PM1B 0x0U
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#define S3_PKG_RESERVED 0x0U
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</S3_INFO>
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<S5_INFO>
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#define S5_PKG_VAL_PM1A 0x7U
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#define S5_PKG_VAL_PM1B 0U
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#define S5_PKG_RESERVED 0x0U
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</S5_INFO>
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<DRHD_INFO>
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#define DRHD_COUNT 2U
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#define DRHD0_DEV_CNT 1U
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#define DRHD0_SEGMENT 0U
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#define DRHD0_FLAGS 0U
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#define DRHD0_REG_BASE 0xFED90000UL
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#define DRHD0_IGNORE true
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#define DRHD0_DEVSCOPE0_BUS 0x0U
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#define DRHD0_DEVSCOPE0_PATH 0x10U
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#define DRHD0_DEVSCOPE1_BUS 0x0U
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#define DRHD0_DEVSCOPE1_PATH 0x0U
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#define DRHD0_DEVSCOPE2_BUS 0x0U
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#define DRHD0_DEVSCOPE2_PATH 0x0U
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#define DRHD0_DEVSCOPE3_BUS 0x0U
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#define DRHD0_DEVSCOPE3_PATH 0x0U
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#define DRHD1_DEV_CNT 2U
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#define DRHD1_SEGMENT 0U
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#define DRHD1_FLAGS 1U
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#define DRHD1_REG_BASE 0xFED91000UL
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#define DRHD1_IGNORE false
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#define DRHD1_DEVSCOPE0_BUS 0x0U
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#define DRHD1_DEVSCOPE0_PATH 0xf7U
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#define DRHD1_DEVSCOPE1_BUS 0x0U
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#define DRHD1_DEVSCOPE1_PATH 0xf6U
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#define DRHD1_DEVSCOPE2_BUS 0x0U
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#define DRHD1_DEVSCOPE2_PATH 0x0U
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#define DRHD1_DEVSCOPE3_BUS 0x0U
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#define DRHD1_DEVSCOPE3_PATH 0x0U
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#define DRHD1_IOAPIC_ID 2U
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#define DRHD2_DEV_CNT 0U
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#define DRHD2_SEGMENT 0U
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#define DRHD2_FLAGS 0U
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#define DRHD2_REG_BASE 0x00UL
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#define DRHD2_IGNORE false
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#define DRHD2_DEVSCOPE0_BUS 0x0U
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#define DRHD2_DEVSCOPE0_PATH 0x0U
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#define DRHD2_DEVSCOPE1_BUS 0x0U
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#define DRHD2_DEVSCOPE1_PATH 0x0U
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#define DRHD2_DEVSCOPE2_BUS 0x0U
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#define DRHD2_DEVSCOPE2_PATH 0x0U
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#define DRHD2_DEVSCOPE3_BUS 0x0U
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#define DRHD2_DEVSCOPE3_PATH 0x0U
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#define DRHD3_DEV_CNT 0U
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#define DRHD3_SEGMENT 0U
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#define DRHD3_FLAGS 0U
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#define DRHD3_REG_BASE 0x00UL
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#define DRHD3_IGNORE false
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#define DRHD3_DEVSCOPE0_BUS 0x0U
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#define DRHD3_DEVSCOPE0_PATH 0x0U
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#define DRHD3_DEVSCOPE1_BUS 0x0U
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#define DRHD3_DEVSCOPE1_PATH 0x0U
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#define DRHD3_DEVSCOPE2_BUS 0x0U
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#define DRHD3_DEVSCOPE2_PATH 0x0U
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#define DRHD3_DEVSCOPE3_BUS 0x0U
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#define DRHD3_DEVSCOPE3_PATH 0x0U
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</DRHD_INFO>
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<CPU_BRAND>
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"Intel(R) Core(TM) i7-8565U CPU @ 1.80GHz"
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</CPU_BRAND>
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<CX_INFO>
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{{SPACE_FFixedHW, 0x01U, 0x02U, 0x01U, 0x00UL}, 0x01U, 0x01U, 0x00U}, /* C1 */
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{{SPACE_FFixedHW, 0x01U, 0x02U, 0x01U, 0x33UL}, 0x02U, 0x97U, 0x00U}, /* C2 */
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{{SPACE_FFixedHW, 0x01U, 0x02U, 0x01U, 0x60UL}, 0x03U, 0x40AU, 0x00U}, /* C3 */
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</CX_INFO>
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<PX_INFO>
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{0x835UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002E00UL, 0x002E00UL}, /* P0 */
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{0x834UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001500UL, 0x001500UL}, /* P1 */
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{0x7D0UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001400UL, 0x001400UL}, /* P2 */
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{0x76CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001300UL, 0x001300UL}, /* P3 */
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{0x708UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001200UL, 0x001200UL}, /* P4 */
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{0x6A4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001100UL, 0x001100UL}, /* P5 */
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{0x640UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001000UL, 0x001000UL}, /* P6 */
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{0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P7 */
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{0x578UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000E00UL, 0x000E00UL}, /* P8 */
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{0x514UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000D00UL, 0x000D00UL}, /* P9 */
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</PX_INFO>
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<CLOS_INFO>
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clos supported by cache:False
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clos max:0
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</CLOS_INFO>
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<SYSTEM_RAM_INFO>
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00001000-0005efff : System RAM
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00060000-0009ffff : System RAM
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00100000-3fffffff : System RAM
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40400000-826f5017 : System RAM
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826f5018-82705657 : System RAM
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82705658-82706017 : System RAM
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82706018-82716057 : System RAM
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82716058-85b5dfff : System RAM
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85b60000-8bfbbfff : System RAM
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8ceff000-8cefffff : System RAM
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100000000-26dffffff : System RAM
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</SYSTEM_RAM_INFO>
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<BLOCK_DEVICE_INFO>
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/dev/nvme0n1p3: TYPE="ext4"
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/dev/sda3: TYPE="ext4"
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</BLOCK_DEVICE_INFO>
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<TTYS_INFO>
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seri:/dev/ttyS0 type:portio base:0x3F8 irq:4
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seri:/dev/ttyS1 type:portio base:0x2F8 irq:3
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seri:/dev/ttyS2 type:portio base:0x3E8 irq:7
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seri:/dev/ttyS3 type:portio base:0x2E8 irq:7
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</TTYS_INFO>
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<AVAILABLE_IRQ_INFO>
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6, 10, 11, 13, 14, 15
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</AVAILABLE_IRQ_INFO>
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<TOTAL_MEM_INFO>
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8105908 kB
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</TOTAL_MEM_INFO>
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<CPU_PROCESSOR_INFO>
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0, 1, 2, 3
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</CPU_PROCESSOR_INFO>
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</acrn-config>

‎misc/acrn-config/xmls/config-xmls/whl-ipc-i7/hybrid.xml

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<acrn-config board="whl-ipc-i7" scenario="hybrid">
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<vm id="0">
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<load_order desc="Specify the VM by its load order: PRE_LAUNCHED_VM, SOS_VM or POST_LAUNCHED_VM." readonly="true">PRE_LAUNCHED_VM</load_order>
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<name desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">ACRN PRE-LAUNCHED VM0</name>
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<uuid configurable="0" desc="vm uuid">fc836901-8685-4bc0-8b71-6e31dc36fa47</uuid>
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<guest_flags desc="Select all applicable flags for the VM" multiselect="true">
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<guest_flag>GUEST_FLAG_HIGHEST_SEVERITY</guest_flag>
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</guest_flags>
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<vcpu_affinity desc="vCPU affinity map. Each vCPU will pin to the selected pCPU ID. Please make sure each vCPU pin to different pCPU.">
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<pcpu_id>3</pcpu_id>
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</vcpu_affinity>
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<clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">0</clos>
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<epc_section desc="epc section">
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<base desc="SGX EPC section base, must be page aligned">0</base>
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<size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
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</epc_section>
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<memory>
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<start_hpa desc="The start physical address in host for the VM">0x100000000</start_hpa>
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<size desc="The memory size in Bytes for the VM">0x20000000</size>
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</memory>
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<os_config>
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<name desc="Specify the OS name of VM, currently it is not referenced by hypervisor code.">Zephyr</name>
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<kern_type desc="Specify the kernel image type so that hypervisor could load it correctly. Currently support KERNEL_BZIMAGE and KERNEL_ZEPHYR.">KERNEL_ZEPHYR</kern_type>
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<kern_mod desc="The tag for kernel image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline.">Zephyr_RawImage</kern_mod>
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<bootargs desc="Specify kernel boot arguments"></bootargs>
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<kern_load_addr desc="The loading address in host memory for the VM kernel">0x100000</kern_load_addr>
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<kern_entry_addr desc="The entry address in host memory for the VM kernel">0x100000</kern_entry_addr>
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</os_config>
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<vuart id="0">
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<type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
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<base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
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<irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
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</vuart>
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<vuart id="1">
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<type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
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<base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM2_BASE</base>
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<irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
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<target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
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<target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
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</vuart>
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<pci_dev_num configurable="0" desc="pci devices number"></pci_dev_num>
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<pci_devs configurable="0" desc="pci devices list"></pci_devs>
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</vm>
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<vm id="1">
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<load_order desc="Specify the VM by its load order: PRE_LAUNCHED_VM, SOS_VM or POST_LAUNCHED_VM." readonly="true">SOS_VM</load_order>
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<name desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">ACRN SOS VM</name>
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<uuid configurable="0" desc="vm uuid">dbbbd434-7a57-4216-a12c-2201f1ab0240</uuid>
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<guest_flags desc="Select all applicable flags for the VM" multiselect="true">
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<guest_flag>0</guest_flag>
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</guest_flags>
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<clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">0</clos>
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<memory>
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<start_hpa configurable="0" desc="The start physical address in host for the VM">0</start_hpa>
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<size configurable="0" desc="The memory size in Bytes for the VM">CONFIG_SOS_RAM_SIZE</size>
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</memory>
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<os_config>
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<name desc="Specify the OS name of VM, currently it is not referenced by hypervisor code.">ACRN Service OS</name>
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<kern_type desc="Specify the kernel image type so that hypervisor could load it correctly. Currently support KERNEL_BZIMAGE and KERNEL_ZEPHYR.">KERNEL_BZIMAGE</kern_type>
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<kern_mod desc="The tag for kernel image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline.">Linux_bzImage</kern_mod>
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<bootargs configurable="0" desc="Specify kernel boot arguments">SOS_VM_BOOTARGS</bootargs>
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</os_config>
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<vuart id="0">
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<type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
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<base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address." readonly="true">SOS_COM1_BASE</base>
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<irq configurable="0" desc="vCOM1 irq">SOS_COM1_IRQ</irq>
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</vuart>
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<vuart id="1">
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<type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
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<base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">SOS_COM2_BASE</base>
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<irq configurable="0" desc="vCOM2 irq">SOS_COM2_IRQ</irq>
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<target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
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<target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
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</vuart>
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<pci_dev_num configurable="0" desc="pci devices number">SOS_EMULATED_PCI_DEV_NUM</pci_dev_num>
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<pci_devs configurable="0" desc="pci devices list">sos_pci_devs</pci_devs>
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<board_private>
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<rootfs desc="rootfs for Linux kernel">/dev/sda3</rootfs>
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<console desc="ttyS console for Linux kernel">/dev/ttyS0</console>
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<bootargs desc="Specify kernel boot arguments">
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rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3
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i915.nuclear_pageflip=1 i915.avail_planes_per_pipe=0x01070F i915.domain_plane_owners=0x011100001111 i915.enable_gvt=1
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hvlog=2M@0x1fe00000 memmap=0x200000$0x1fe00000
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</bootargs>
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</board_private>
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</vm>
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<vm id="2">
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<load_order desc="Specify the VM by its load order: PRE_LAUNCHED_VM, SOS_VM or POST_LAUNCHED_VM." readonly="true">POST_LAUNCHED_VM</load_order>
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<uuid configurable="0" desc="vm uuid">d2795438-25d6-11e8-864e-cb7a18b34643</uuid>
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<guest_flags desc="Select all applicable flags for the VM" multiselect="true">
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<guest_flag>0</guest_flag>
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</guest_flags>
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<vcpu_affinity desc="vCPU affinity map. Each vCPU will pin to the selected pCPU ID. Please make sure each vCPU pin to different pCPU.">
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<pcpu_id>2</pcpu_id>
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</vcpu_affinity>
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<clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">0</clos>
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<epc_section desc="epc section">
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<base desc="SGX EPC section base, must be page aligned">0</base>
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<size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
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</epc_section>
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<vuart id="0">
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<type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
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<base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
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<irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
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</vuart>
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<vuart id="1">
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<type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
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<base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
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<irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
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<target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
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<target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">0</target_uart_id>
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</vuart>
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</vm>
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</acrn-config>

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