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8 | 8 |
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9 | 9 | /* The table includes cpu px info of Intel A3960 SoC */
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10 | 10 | static const struct cpu_px_data px_a3960[] = {
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11 |
| - {0x960, 0, 0xA, 0xA, 0x1800, 0x1800}, /* P0 */ |
12 |
| - {0x8FC, 0, 0xA, 0xA, 0x1700, 0x1700}, /* P1 */ |
13 |
| - {0x898, 0, 0xA, 0xA, 0x1600, 0x1600}, /* P2 */ |
14 |
| - {0x834, 0, 0xA, 0xA, 0x1500, 0x1500}, /* P3 */ |
15 |
| - {0x7D0, 0, 0xA, 0xA, 0x1400, 0x1400}, /* P4 */ |
16 |
| - {0x76C, 0, 0xA, 0xA, 0x1300, 0x1300}, /* P5 */ |
17 |
| - {0x708, 0, 0xA, 0xA, 0x1200, 0x1200}, /* P6 */ |
18 |
| - {0x6A4, 0, 0xA, 0xA, 0x1100, 0x1100}, /* P7 */ |
19 |
| - {0x640, 0, 0xA, 0xA, 0x1000, 0x1000}, /* P8 */ |
20 |
| - {0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P9 */ |
21 |
| - {0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P10 */ |
22 |
| - {0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P11 */ |
23 |
| - {0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P12 */ |
24 |
| - {0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P13 */ |
25 |
| - {0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P14 */ |
26 |
| - {0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P15 */ |
27 |
| - {0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P16 */ |
| 11 | + {0x960UL, 0UL, 0xAUL, 0xAUL, 0x1800UL, 0x1800UL}, /* P0 */ |
| 12 | + {0x8FCUL, 0UL, 0xAUL, 0xAUL, 0x1700UL, 0x1700UL}, /* P1 */ |
| 13 | + {0x898UL, 0UL, 0xAUL, 0xAUL, 0x1600UL, 0x1600UL}, /* P2 */ |
| 14 | + {0x834UL, 0UL, 0xAUL, 0xAUL, 0x1500UL, 0x1500UL}, /* P3 */ |
| 15 | + {0x7D0UL, 0UL, 0xAUL, 0xAUL, 0x1400UL, 0x1400UL}, /* P4 */ |
| 16 | + {0x76CUL, 0UL, 0xAUL, 0xAUL, 0x1300UL, 0x1300UL}, /* P5 */ |
| 17 | + {0x708UL, 0UL, 0xAUL, 0xAUL, 0x1200UL, 0x1200UL}, /* P6 */ |
| 18 | + {0x6A4UL, 0UL, 0xAUL, 0xAUL, 0x1100UL, 0x1100UL}, /* P7 */ |
| 19 | + {0x640UL, 0UL, 0xAUL, 0xAUL, 0x1000UL, 0x1000UL}, /* P8 */ |
| 20 | + {0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P9 */ |
| 21 | + {0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P10 */ |
| 22 | + {0x514UL, 0UL, 0xAUL, 0xAUL, 0x0D00UL, 0x0D00UL}, /* P11 */ |
| 23 | + {0x4B0UL, 0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P12 */ |
| 24 | + {0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P13 */ |
| 25 | + {0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P14 */ |
| 26 | + {0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P15 */ |
| 27 | + {0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL} /* P16 */ |
28 | 28 | };
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29 | 29 |
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30 | 30 | /* The table includes cpu cx info of Intel A3960 SoC */
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31 | 31 | static const struct cpu_cx_data cx_a3960[] = {
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32 |
| - {{SPACE_FFixedHW, 0x0, 0, 0, 0}, 0x1, 0x1, 0x3E8}, /* C1 */ |
33 |
| - {{SPACE_SYSTEM_IO, 0x8, 0, 0, 0x415}, 0x2, 0x32, 0x0A}, /* C2 */ |
34 |
| - {{SPACE_SYSTEM_IO, 0x8, 0, 0, 0x419}, 0x3, 0x96, 0x0A} /* C3 */ |
| 32 | + {{SPACE_FFixedHW, 0x0U, 0U, 0U, 0UL}, 0x1U, 0x1U, 0x3E8UL}, /* C1 */ |
| 33 | + {{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x415UL}, 0x2U, 0x32U, 0x0AUL}, /* C2 */ |
| 34 | + {{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x419UL}, 0x3U, 0x96U, 0x0AUL} /* C3 */ |
35 | 35 | };
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36 | 36 |
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37 | 37 | /* The table includes cpu px info of Intel A3950 SoC */
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38 | 38 | static const struct cpu_px_data px_a3950[] = {
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39 |
| - {0x7D0, 0, 0xA, 0xA, 0x1400, 0x1400}, /* P0 */ |
40 |
| - {0x76C, 0, 0xA, 0xA, 0x1300, 0x1300}, /* P1 */ |
41 |
| - {0x708, 0, 0xA, 0xA, 0x1200, 0x1200}, /* P2 */ |
42 |
| - {0x6A4, 0, 0xA, 0xA, 0x1100, 0x1100}, /* P3 */ |
43 |
| - {0x640, 0, 0xA, 0xA, 0x1000, 0x1000}, /* P4 */ |
44 |
| - {0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P5 */ |
45 |
| - {0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P6 */ |
46 |
| - {0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P7 */ |
47 |
| - {0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P8 */ |
48 |
| - {0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P9 */ |
49 |
| - {0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P10 */ |
50 |
| - {0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P11 */ |
51 |
| - {0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P12 */ |
| 39 | + {0x7D0UL, 0UL, 0xAUL, 0xAUL, 0x1400UL, 0x1400UL}, /* P0 */ |
| 40 | + {0x76CUL, 0UL, 0xAUL, 0xAUL, 0x1300UL, 0x1300UL}, /* P1 */ |
| 41 | + {0x708UL, 0UL, 0xAUL, 0xAUL, 0x1200UL, 0x1200UL}, /* P2 */ |
| 42 | + {0x6A4UL, 0UL, 0xAUL, 0xAUL, 0x1100UL, 0x1100UL}, /* P3 */ |
| 43 | + {0x640UL, 0UL, 0xAUL, 0xAUL, 0x1000UL, 0x1000UL}, /* P4 */ |
| 44 | + {0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P5 */ |
| 45 | + {0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P6 */ |
| 46 | + {0x514UL, 0UL, 0xAUL, 0xAUL, 0x0D00UL, 0x0D00UL}, /* P7 */ |
| 47 | + {0x4B0UL, 0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P8 */ |
| 48 | + {0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P9 */ |
| 49 | + {0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P10 */ |
| 50 | + {0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P11 */ |
| 51 | + {0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL} /* P12 */ |
52 | 52 | };
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53 | 53 |
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54 | 54 | /* The table includes cpu px info of Intel J3455 SoC */
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55 | 55 | static const struct cpu_px_data px_j3455[] = {
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56 |
| - {0x5DD, 0, 0xA, 0xA, 0x1700, 0x1700}, /* P0 */ |
57 |
| - {0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P1 */ |
58 |
| - {0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P2 */ |
59 |
| - {0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P3 */ |
60 |
| - {0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P4 */ |
61 |
| - {0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P5 */ |
62 |
| - {0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P6 */ |
63 |
| - {0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P7 */ |
64 |
| - {0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P8 */ |
| 56 | + {0x5DDUL, 0UL, 0xAUL, 0xAUL, 0x1700UL, 0x1700UL}, /* P0 */ |
| 57 | + {0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P1 */ |
| 58 | + {0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P2 */ |
| 59 | + {0x514UL, 0UL, 0xAUL, 0xAUL, 0x0D00UL, 0x0D00UL}, /* P3 */ |
| 60 | + {0x4B0UL, 0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P4 */ |
| 61 | + {0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P5 */ |
| 62 | + {0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P6 */ |
| 63 | + {0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P7 */ |
| 64 | + {0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL} /* P8 */ |
65 | 65 | };
|
66 | 66 |
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67 | 67 | /* The table includes cpu cx info of Intel J3455 SoC */
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68 | 68 | static const struct cpu_cx_data cx_j3455[] = {
|
69 |
| - {{SPACE_FFixedHW, 0x1, 0x2, 0x1, 0x01}, 0x1, 0x1, 0x3E8}, /* C1 */ |
70 |
| - {{SPACE_FFixedHW, 0x1, 0x2, 0x1, 0x21}, 0x2, 0x32, 0x0A}, /* C2 */ |
71 |
| - {{SPACE_FFixedHW, 0x1, 0x2, 0x1, 0x60}, 0x3, 0x96, 0x0A} /* C3 */ |
| 69 | + {{SPACE_FFixedHW, 0x1U, 0x2U, 0x1U, 0x01UL}, 0x1U, 0x1U, 0x3E8UL}, /* C1 */ |
| 70 | + {{SPACE_FFixedHW, 0x1U, 0x2U, 0x1U, 0x21UL}, 0x2U, 0x32U, 0x0AUL}, /* C2 */ |
| 71 | + {{SPACE_FFixedHW, 0x1U, 0x2U, 0x1U, 0x60UL}, 0x3U, 0x96U, 0x0AUL} /* C3 */ |
72 | 72 | };
|
73 | 73 |
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74 | 74 | static const struct cpu_state_table {
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@@ -113,7 +113,7 @@ void load_cpu_state_data(void)
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113 | 113 | int tbl_idx;
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114 | 114 | const struct cpu_state_info *state_info;
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115 | 115 |
|
116 |
| - (void)memset(&boot_cpu_data.state_info, 0, |
| 116 | + (void)memset(&boot_cpu_data.state_info, 0U, |
117 | 117 | sizeof(struct cpu_state_info));
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118 | 118 |
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119 | 119 | tbl_idx = get_state_tbl_idx(boot_cpu_data.model_name);
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