hv: vlapic: minor fix for update_msr_bitmap_x2apic_apicv

lifeix · Eddie Dong · commit 4a683ed10ead · 2019-03-25T13:31:51.000-07:00
Shouldn't trap TPR since we always enable "Use TPR shadow" Tracked-On: #1842 Signed-off-by: Li, Fei1 <fei1.li@intel.com>
diff --git a/hypervisor/arch/x86/guest/vmsr.c b/hypervisor/arch/x86/guest/vmsr.c
@@ -640,10 +640,11 @@ void update_msr_bitmap_x2apic_apicv(const struct acrn_vcpu *vcpu)
 		 * writes to them are virtualized with Register Virtualization
 		 * Refer to Section 29.1 in Intel SDM Vol. 3
 		 */
-		enable_msr_interception(msr_bitmap, MSR_IA32_EXT_APIC_TPR, INTERCEPT_DISABLE);
 		enable_msr_interception(msr_bitmap, MSR_IA32_EXT_APIC_EOI, INTERCEPT_READ);
 		enable_msr_interception(msr_bitmap, MSR_IA32_EXT_APIC_SELF_IPI, INTERCEPT_READ);
 	}
+
+	enable_msr_interception(msr_bitmap, MSR_IA32_EXT_APIC_TPR, INTERCEPT_DISABLE);
 }
 
 /*

Original file line number	Diff line number	Diff line change
`@@ -640,10 +640,11 @@ void update_msr_bitmap_x2apic_apicv(const struct acrn_vcpu *vcpu)`
`640`	`640`	`* writes to them are virtualized with Register Virtualization`
`641`	`641`	`* Refer to Section 29.1 in Intel SDM Vol. 3`
`642`	`642`	`*/`
`643`		`- enable_msr_interception(msr_bitmap, MSR_IA32_EXT_APIC_TPR, INTERCEPT_DISABLE);`
`644`	`643`	`enable_msr_interception(msr_bitmap, MSR_IA32_EXT_APIC_EOI, INTERCEPT_READ);`
`645`	`644`	`enable_msr_interception(msr_bitmap, MSR_IA32_EXT_APIC_SELF_IPI, INTERCEPT_READ);`
`646`	`645`	`}`
	`646`	`+`
	`647`	`+ enable_msr_interception(msr_bitmap, MSR_IA32_EXT_APIC_TPR, INTERCEPT_DISABLE);`
`647`	`648`	`}`
`648`	`649`
`649`	`650`	`/*`