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binbinwu1lijinxia
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hv: vtd: fix potential buffer overflow in suspend/resume
In current code of suspend_iommu/resume_iommu, there is potential buffer overflow according to the code. This patch put the buffer to struct dmar_drhd_rt, so that no need to access the buffer via index. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Tracked-On: #1252 Acked-by: Eddie Dong <eddie.dong@intel.com>
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hypervisor/arch/x86/vtd.c

Lines changed: 12 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,10 @@
3030
#define ROOT_ENTRY_LOWER_CTP_POS (12U)
3131
#define ROOT_ENTRY_LOWER_CTP_MASK (0xFFFFFFFFFFFFFUL)
3232

33+
/* 4 iommu fault register state */
34+
#define IOMMU_FAULT_REGISTER_STATE_NUM 4U
35+
#define IOMMU_FAULT_REGISTER_SIZE 4U
36+
3337
#define CTX_ENTRY_UPPER_AW_POS (0U)
3438
#define CTX_ENTRY_UPPER_AW_MASK \
3539
(0x7UL << CTX_ENTRY_UPPER_AW_POS)
@@ -118,6 +122,7 @@ struct dmar_drhd_rt {
118122
uint16_t cap_num_fault_regs;
119123
uint16_t cap_fault_reg_offset;
120124
uint16_t ecap_iotlb_offset;
125+
uint32_t fault_state[IOMMU_FAULT_REGISTER_STATE_NUM]; /* 32bit registers */
121126
};
122127

123128
struct dmar_root_entry {
@@ -1205,16 +1210,11 @@ void disable_iommu(void)
12051210
}
12061211
}
12071212

1208-
/* 4 iommu fault register state */
1209-
#define IOMMU_FAULT_REGISTER_STATE_NUM 4U
1210-
static uint32_t
1211-
iommu_fault_state[CONFIG_MAX_IOMMU_NUM][IOMMU_FAULT_REGISTER_STATE_NUM];
1212-
12131213
void suspend_iommu(void)
12141214
{
12151215
struct dmar_drhd_rt *dmar_unit;
12161216
struct list_head *pos;
1217-
uint32_t i, iommu_idx = 0U;
1217+
uint32_t i;
12181218

12191219
list_for_each(pos, &dmar_drhd_units) {
12201220
dmar_unit = list_entry(pos, struct dmar_drhd_rt, list);
@@ -1230,29 +1230,20 @@ void suspend_iommu(void)
12301230

12311231
/* save IOMMU fault register state */
12321232
for (i = 0U; i < IOMMU_FAULT_REGISTER_STATE_NUM; i++) {
1233-
iommu_fault_state[iommu_idx][i] =
1234-
iommu_read32(dmar_unit, DMAR_FECTL_REG +
1235-
(i * IOMMU_FAULT_REGISTER_STATE_NUM));
1233+
dmar_unit->fault_state[i] = iommu_read32(dmar_unit,
1234+
DMAR_FECTL_REG + (i * IOMMU_FAULT_REGISTER_SIZE));
1235+
12361236
}
12371237
/* disable translation */
12381238
dmar_disable_translation(dmar_unit);
1239-
1240-
/* If the number of real iommu devices is larger than we
1241-
* defined in kconfig.
1242-
*/
1243-
if (iommu_idx > CONFIG_MAX_IOMMU_NUM) {
1244-
pr_err("iommu dev number is larger than pre-defined");
1245-
break;
1246-
}
1247-
iommu_idx++;
12481239
}
12491240
}
12501241

12511242
void resume_iommu(void)
12521243
{
12531244
struct dmar_drhd_rt *dmar_unit;
12541245
struct list_head *pos;
1255-
uint32_t i, iommu_idx = 0U;
1246+
uint32_t i;
12561247

12571248
/* restore IOMMU fault register state */
12581249
list_for_each(pos, &dmar_drhd_units) {
@@ -1273,20 +1264,11 @@ void resume_iommu(void)
12731264
/* restore IOMMU fault register state */
12741265
for (i = 0U; i < IOMMU_FAULT_REGISTER_STATE_NUM; i++) {
12751266
iommu_write32(dmar_unit, DMAR_FECTL_REG +
1276-
(i * IOMMU_FAULT_REGISTER_STATE_NUM),
1277-
iommu_fault_state[iommu_idx][i]);
1267+
(i * IOMMU_FAULT_REGISTER_SIZE),
1268+
dmar_unit->fault_state[i]);
12781269
}
12791270
/* enable translation */
12801271
dmar_enable_translation(dmar_unit);
1281-
1282-
/* If the number of real iommu devices is larger than we
1283-
* defined in kconfig.
1284-
*/
1285-
if (iommu_idx > CONFIG_MAX_IOMMU_NUM) {
1286-
pr_err("iommu dev number is larger than pre-defined");
1287-
break;
1288-
}
1289-
iommu_idx++;
12901272
}
12911273
}
12921274

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