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lifeixjren1
lifeix
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jren1
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hv: vlapic: simple vlapic_rd/wr input
Remove unnecessary input parameters Signed-off-by: Li, Fei1 <fei1.li@intel.com>
1 parent 57152d0 commit 5a47c26

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3 files changed

+38
-42
lines changed

3 files changed

+38
-42
lines changed

‎hypervisor/arch/x86/guest/vlapic.c

Lines changed: 33 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -110,10 +110,10 @@ static void *apicv_apic_access_addr;
110110

111111
static int
112112
vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,
113-
uint64_t data, bool *retu);
113+
uint64_t data);
114114
static int
115115
vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
116-
uint64_t *data, bool *retu);
116+
uint64_t *data);
117117

118118
static int
119119
apicv_set_intr_ready(struct vlapic *vlapic, int vector, bool level);
@@ -370,7 +370,7 @@ vlapic_dcr_write_handler(struct vlapic *vlapic)
370370

371371
divisor = vlapic_timer_divisor(lapic->dcr_timer);
372372
dev_dbg(ACRN_DBG_LAPIC, "vlapic dcr_timer=%#x, divisor=%d",
373-
lapic->dcr_timer, divisor);
373+
lapic->dcr_timer, divisor);
374374

375375
/*
376376
* Update the timer frequency and the timer period.
@@ -1095,7 +1095,7 @@ vlapic_get_cr8(struct vlapic *vlapic)
10951095
}
10961096

10971097
static int
1098-
vlapic_icrlo_write_handler(struct vlapic *vlapic, bool *retu)
1098+
vlapic_icrlo_write_handler(struct vlapic *vlapic)
10991099
{
11001100
int i;
11011101
bool phys;
@@ -1219,7 +1219,6 @@ vlapic_icrlo_write_handler(struct vlapic *vlapic, bool *retu)
12191219
target_vcpu->vm->attr.id);
12201220
schedule_vcpu(target_vcpu);
12211221

1222-
*retu = true;
12231222
return 0;
12241223
}
12251224
}
@@ -1342,7 +1341,7 @@ vlapic_svr_write_handler(struct vlapic *vlapic)
13421341

13431342
static int
13441343
vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
1345-
uint64_t *data, bool *retu)
1344+
uint64_t *data)
13461345
{
13471346
struct lapic *lapic = vlapic->apic_page;
13481347
int i;
@@ -1446,7 +1445,6 @@ vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
14461445
case APIC_OFFSET_RRR:
14471446
default:
14481447
*data = 0;
1449-
*retu = true;
14501448
break;
14511449
}
14521450
done:
@@ -1457,7 +1455,7 @@ vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
14571455

14581456
static int
14591457
vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,
1460-
uint64_t data, bool *retu)
1458+
uint64_t data)
14611459
{
14621460
struct lapic *lapic = vlapic->apic_page;
14631461
uint32_t *regptr;
@@ -1508,7 +1506,7 @@ vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,
15081506
break;
15091507
case APIC_OFFSET_ICR_LOW:
15101508
lapic->icr_lo = data;
1511-
retval = vlapic_icrlo_write_handler(vlapic, retu);
1509+
retval = vlapic_icrlo_write_handler(vlapic);
15121510
break;
15131511
case APIC_OFFSET_ICR_HI:
15141512
lapic->icr_hi = data;
@@ -1927,29 +1925,31 @@ static int tsc_periodic_time(uint64_t data)
19271925
}
19281926

19291927
int
1930-
vlapic_rdmsr(struct vcpu *vcpu, uint32_t msr, uint64_t *rval,
1931-
bool *retu)
1928+
vlapic_rdmsr(struct vcpu *vcpu, uint32_t msr, uint64_t *rval)
19321929
{
1933-
int error;
1930+
int error = 0;
19341931
uint32_t offset;
19351932
struct vlapic *vlapic;
19361933

19371934
dev_dbg(ACRN_DBG_LAPIC, "cpu[%d] rdmsr: %x", vcpu->vcpu_id, msr);
19381935
vlapic = vcpu->arch_vcpu.vlapic;
19391936

1940-
if (msr == MSR_IA32_APIC_BASE) {
1937+
switch (msr) {
1938+
case MSR_IA32_APIC_BASE:
19411939
*rval = vlapic_get_apicbase(vlapic);
1942-
error = 0;
1943-
} else {
1940+
break;
1941+
1942+
default:
19441943
offset = x2apic_msr_to_regoff(msr);
1945-
error = vlapic_read(vlapic, 0, offset, rval, retu);
1944+
error = vlapic_read(vlapic, 0, offset, rval);
1945+
break;
19461946
}
19471947

19481948
return error;
19491949
}
19501950

19511951
int
1952-
vlapic_wrmsr(struct vcpu *vcpu, uint32_t msr, uint64_t val, bool *retu)
1952+
vlapic_wrmsr(struct vcpu *vcpu, uint32_t msr, uint64_t val)
19531953
{
19541954
int error;
19551955
uint32_t offset;
@@ -1959,9 +1959,12 @@ vlapic_wrmsr(struct vcpu *vcpu, uint32_t msr, uint64_t val, bool *retu)
19591959
vlapic = vcpu->arch_vcpu.vlapic;
19601960
lapic = vlapic->apic_page;
19611961

1962-
if (msr == MSR_IA32_APIC_BASE) {
1962+
switch (msr) {
1963+
case MSR_IA32_APIC_BASE:
19631964
error = vlapic_set_apicbase(vlapic, val);
1964-
} else if (msr == MSR_IA32_TSC_DEADLINE) {
1965+
break;
1966+
1967+
case MSR_IA32_TSC_DEADLINE:
19651968
error = 0;
19661969
if (!VLAPIC_TSCDEADLINE(lapic->lvt_timer))
19671970
return error;
@@ -1981,9 +1984,12 @@ vlapic_wrmsr(struct vcpu *vcpu, uint32_t msr, uint64_t val, bool *retu)
19811984
error = -1;
19821985
}
19831986
}
1984-
} else {
1987+
break;
1988+
1989+
default:
19851990
offset = x2apic_msr_to_regoff(msr);
1986-
error = vlapic_write(vlapic, 0, offset, val, retu);
1991+
error = vlapic_write(vlapic, 0, offset, val);
1992+
break;
19871993
}
19881994

19891995
dev_dbg(ACRN_DBG_LAPIC, "cpu[%d] wrmsr: %x val=%#x",
@@ -1997,7 +2003,6 @@ vlapic_mmio_write(struct vcpu *vcpu, uint64_t gpa, uint64_t wval, int size)
19972003
int error;
19982004
uint64_t off;
19992005
struct vlapic *vlapic;
2000-
bool arg;
20012006

20022007
off = gpa - DEFAULT_APIC_BASE;
20032008

@@ -2009,7 +2014,7 @@ vlapic_mmio_write(struct vcpu *vcpu, uint64_t gpa, uint64_t wval, int size)
20092014
return -EINVAL;
20102015

20112016
vlapic = vcpu->arch_vcpu.vlapic;
2012-
error = vlapic_write(vlapic, 1, off, wval, &arg);
2017+
error = vlapic_write(vlapic, 1, off, wval);
20132018
return error;
20142019
}
20152020

@@ -2020,7 +2025,6 @@ vlapic_mmio_read(struct vcpu *vcpu, uint64_t gpa, uint64_t *rval,
20202025
int error;
20212026
uint64_t off;
20222027
struct vlapic *vlapic;
2023-
bool arg;
20242028

20252029
off = gpa - DEFAULT_APIC_BASE;
20262030

@@ -2034,7 +2038,7 @@ vlapic_mmio_read(struct vcpu *vcpu, uint64_t gpa, uint64_t *rval,
20342038
return -EINVAL;
20352039

20362040
vlapic = vcpu->arch_vcpu.vlapic;
2037-
error = vlapic_read(vlapic, 1, off, rval, &arg);
2041+
error = vlapic_read(vlapic, 1, off, rval);
20382042
return error;
20392043
}
20402044

@@ -2339,7 +2343,6 @@ apicv_inject_pir(struct vlapic *vlapic)
23392343

23402344
int apic_access_vmexit_handler(struct vcpu *vcpu)
23412345
{
2342-
bool ret;
23432346
int access_type, offset;
23442347
uint64_t qual;
23452348
struct vlapic *vlapic;
@@ -2356,9 +2359,9 @@ int apic_access_vmexit_handler(struct vcpu *vcpu)
23562359
analyze_instruction(vcpu, &vcpu->mmio);
23572360
if (access_type == 1) {
23582361
if (!emulate_instruction(vcpu, &vcpu->mmio))
2359-
vlapic_write(vlapic, 1, offset, vcpu->mmio.value, &ret);
2362+
vlapic_write(vlapic, 1, offset, vcpu->mmio.value);
23602363
} else if (access_type == 0) {
2361-
vlapic_read(vlapic, 1, offset, &vcpu->mmio.value, &ret);
2364+
vlapic_read(vlapic, 1, offset, &vcpu->mmio.value);
23622365
emulate_instruction(vcpu, &vcpu->mmio);
23632366
}
23642367

@@ -2397,7 +2400,6 @@ int veoi_vmexit_handler(struct vcpu *vcpu)
23972400

23982401
int apic_write_vmexit_handler(struct vcpu *vcpu)
23992402
{
2400-
bool retu;
24012403
uint64_t qual;
24022404
int error, handled, offset;
24032405
struct vlapic *vlapic = NULL;
@@ -2429,9 +2431,8 @@ int apic_write_vmexit_handler(struct vcpu *vcpu)
24292431
vlapic_esr_write_handler(vlapic);
24302432
break;
24312433
case APIC_OFFSET_ICR_LOW:
2432-
retu = false;
2433-
error = vlapic_icrlo_write_handler(vlapic, &retu);
2434-
if (error != 0 || retu)
2434+
error = vlapic_icrlo_write_handler(vlapic);
2435+
if (error != 0)
24352436
handled = 0;
24362437
break;
24372438
case APIC_OFFSET_CMCI_LVT:

‎hypervisor/arch/x86/guest/vmsr.c

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -229,9 +229,8 @@ int rdmsr_handler(struct vcpu *vcpu)
229229
}
230230
case MSR_IA32_APIC_BASE:
231231
{
232-
bool ret;
233232
/* Read APIC base */
234-
vlapic_rdmsr(vcpu, msr, &v, &ret);
233+
vlapic_rdmsr(vcpu, msr, &v);
235234
break;
236235
}
237236
default:
@@ -270,9 +269,7 @@ int wrmsr_handler(struct vcpu *vcpu)
270269
switch (msr) {
271270
case MSR_IA32_TSC_DEADLINE:
272271
{
273-
bool ret;
274-
/* Write APIC base */
275-
vlapic_wrmsr(vcpu, msr, v, &ret);
272+
vlapic_wrmsr(vcpu, msr, v);
276273
vcpu->guest_msrs[IDX_TSC_DEADLINE] = v;
277274
break;
278275
}
@@ -324,9 +321,7 @@ int wrmsr_handler(struct vcpu *vcpu)
324321
}
325322
case MSR_IA32_APIC_BASE:
326323
{
327-
bool ret;
328-
/* Write APIC base */
329-
vlapic_wrmsr(vcpu, msr, v, &ret);
324+
vlapic_wrmsr(vcpu, msr, v);
330325
break;
331326
}
332327
default:

‎hypervisor/include/arch/x86/guest/vlapic.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -59,8 +59,8 @@ void vlapic_intr_accepted(struct vlapic *vlapic, int vector);
5959
struct vlapic *vm_lapic_from_vcpuid(struct vm *vm, int vcpu_id);
6060
struct vlapic *vm_lapic_from_pcpuid(struct vm *vm, int pcpu_id);
6161
bool vlapic_msr(uint32_t num);
62-
int vlapic_rdmsr(struct vcpu *vcpu, uint32_t msr, uint64_t *rval, bool *retu);
63-
int vlapic_wrmsr(struct vcpu *vcpu, uint32_t msr, uint64_t wval, bool *retu);
62+
int vlapic_rdmsr(struct vcpu *vcpu, uint32_t msr, uint64_t *rval);
63+
int vlapic_wrmsr(struct vcpu *vcpu, uint32_t msr, uint64_t wval);
6464

6565
int vlapic_mmio_read(struct vcpu *vcpu, uint64_t gpa, uint64_t *rval, int size);
6666
int vlapic_mmio_write(struct vcpu *vcpu, uint64_t gpa, uint64_t wval, int size);

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