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HV: add Px Cx support for A3950 SoC
Intel Atom A3950 SoC also can be used in Acrn, and it has same Cx data as Atom A3960 SoC. Signed-off-by: Victor Sun <victor.sun@intel.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com>
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hypervisor/arch/x86/cpu_state_tbl.c

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@@ -34,6 +34,23 @@ struct cpu_cx_data cx_a3960[] = {
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{{SPACE_SYSTEM_IO, 0x8, 0, 0, 0x419}, 0x3, 0x96, 0x0A} /* C3 */
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};
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/* The table includes cpu px info of Intel A3950 SoC */
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struct cpu_px_data px_a3950[] = {
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{0x7D0, 0, 0xA, 0xA, 0x1400, 0x1400}, /* P0 */
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{0x76C, 0, 0xA, 0xA, 0x1300, 0x1300}, /* P1 */
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{0x708, 0, 0xA, 0xA, 0x1200, 0x1200}, /* P2 */
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{0x6A4, 0, 0xA, 0xA, 0x1100, 0x1100}, /* P3 */
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{0x640, 0, 0xA, 0xA, 0x1000, 0x1000}, /* P4 */
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{0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P5 */
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{0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P6 */
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{0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P7 */
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{0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P8 */
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{0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P9 */
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{0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P10 */
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{0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P11 */
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{0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P12 */
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};
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/* The table includes cpu px info of Intel J3455 SoC */
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struct cpu_px_data px_j3455[] = {
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{0x5DD, 0, 0xA, 0xA, 0x1700, 0x1700}, /* P0 */
@@ -62,6 +79,10 @@ struct cpu_state_table {
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{ARRAY_SIZE(px_a3960), px_a3960,
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ARRAY_SIZE(cx_a3960), cx_a3960}
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},
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{"Intel(R) Atom(TM) Processor A3950 @ 1.60GHz",
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{ARRAY_SIZE(px_a3950), px_a3950,
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ARRAY_SIZE(cx_a3960), cx_a3960} /* Cx is same as A3960 */
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},
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{"Intel(R) Celeron(R) CPU J3455 @ 1.50GHz",
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{ARRAY_SIZE(px_j3455), px_j3455,
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ARRAY_SIZE(cx_j3455), cx_j3455}

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