hv:Rename port/mmio read and write APIs

mingqiangchi · lijinxia · commit 61782d743013 · 2018-08-02T14:03:38.000+08:00
mmio_write_long --&gt; mmio_write32
mmio_write_word --&gt; mmio_write16
mmio_write_byte --&gt; mmio_write8
mmio_read_long  --&gt; mmio_read32
mmio_read_word  --&gt; mmio_read16
mmio_read_byte  --&gt; mmio_read8

io_write_long --&gt; pio_write32
io_write_word --&gt; pio_write16
io_write_byte --&gt; pio_write8
io_read_long  --&gt; pio_read32
io_read_word  --&gt; pio_read16
io_read_byte  --&gt; pio_read8
io_write      --&gt; pio_write
io_read       --&gt; pio_read

setl --&gt; set32
setw --&gt; set16
setb --&gt; set8

igned-off-by: Mingqiang Chi &lt;mingqiang.chi@intel.com&gt;
diff --git a/hypervisor/arch/x86/debug/reboot.c b/hypervisor/arch/x86/debug/reboot.c
@@ -7,6 +7,6 @@
 
 int warm_reboot(void)
 {
-	io_write_byte(0x6, 0xcf9);
+	pio_write8(0x6, 0xcf9);
 	return 0;
 }
diff --git a/hypervisor/arch/x86/guest/pm.c b/hypervisor/arch/x86/guest/pm.c
@@ -137,7 +137,7 @@ static inline uint8_t get_slp_typx(uint32_t pm1_cnt)
 static uint32_t pm1ab_io_read(__unused struct vm_io_handler *hdlr,
 		__unused struct vm *vm, uint16_t addr, size_t width)
 {
-	uint32_t val = io_read(addr, width);
+	uint32_t val = pio_read(addr, width);
 
 	if (host_enter_s3_success == 0U) {
 		/* If host S3 enter failes, we should set BIT_WAK_STS
@@ -186,7 +186,7 @@ static void pm1ab_io_write(__unused struct vm_io_handler *hdlr,
 		}
 	}
 
-	io_write(v, addr, width);
+	pio_write(v, addr, width);
 }
 
 static void
diff --git a/hypervisor/arch/x86/ioapic.c b/hypervisor/arch/x86/ioapic.c
@@ -99,9 +99,9 @@ ioapic_read_reg32(const void *ioapic_base, const uint32_t offset)
 	spinlock_irqsave_obtain(&ioapic_lock);
 
 	/* Write IOREGSEL */
-	mmio_write_long(offset, (void *)ioapic_base + IOAPIC_REGSEL);
+	mmio_write32(offset, (void *)ioapic_base + IOAPIC_REGSEL);
 	/* Read  IOWIN */
-	v = mmio_read_long((void *)ioapic_base + IOAPIC_WINDOW);
+	v = mmio_read32((void *)ioapic_base + IOAPIC_WINDOW);
 
 	spinlock_irqrestore_release(&ioapic_lock);
 	return v;
@@ -116,9 +116,9 @@ ioapic_write_reg32(const void *ioapic_base,
 	spinlock_irqsave_obtain(&ioapic_lock);
 
 	/* Write IOREGSEL */
-	mmio_write_long(offset, (void *)ioapic_base + IOAPIC_REGSEL);
+	mmio_write32(offset, (void *)ioapic_base + IOAPIC_REGSEL);
 	/* Write IOWIN */
-	mmio_write_long(value, (void *)ioapic_base + IOAPIC_WINDOW);
+	mmio_write32(value, (void *)ioapic_base + IOAPIC_WINDOW);
 
 	spinlock_irqrestore_release(&ioapic_lock);
 }
diff --git a/hypervisor/arch/x86/irq.c b/hypervisor/arch/x86/irq.c
@@ -157,8 +157,8 @@ static void _irq_desc_free_vector(uint32_t irq)
 
 static void disable_pic_irq(void)
 {
-	io_write_byte(0xffU, 0xA1U);
-	io_write_byte(0xffU, 0x21U);
+	pio_write8(0xffU, 0xA1U);
+	pio_write8(0xffU, 0x21U);
 }
 
 static bool
diff --git a/hypervisor/arch/x86/lapic.c b/hypervisor/arch/x86/lapic.c
@@ -143,15 +143,15 @@ static inline uint32_t read_lapic_reg32(uint32_t offset)
 	if (offset < 0x20U || offset > 0x3ffU)
 		return 0;
 
-	return mmio_read_long(lapic_info.xapic.vaddr + offset);
+	return mmio_read32(lapic_info.xapic.vaddr + offset);
 }
 
 inline void write_lapic_reg32(uint32_t offset, uint32_t value)
 {
 	if (offset < 0x20U || offset > 0x3ffU)
 		return;
 
-	mmio_write_long(value, lapic_info.xapic.vaddr + offset);
+	mmio_write32(value, lapic_info.xapic.vaddr + offset);
 }
 
 static void clear_lapic_isr(void)
diff --git a/hypervisor/arch/x86/pm.c b/hypervisor/arch/x86/pm.c
@@ -24,19 +24,19 @@ static void acpi_gas_write(struct acpi_generic_address *gas, uint32_t val)
 	uint16_t val16 = (uint16_t)val;
 
 	if (gas->space_id == SPACE_SYSTEM_MEMORY)
-		mmio_write_word(val16, HPA2HVA(gas->address));
+		mmio_write16(val16, HPA2HVA(gas->address));
 	else
-		io_write_word(val16, (uint16_t)gas->address);
+		pio_write16(val16, (uint16_t)gas->address);
 }
 
 static uint32_t acpi_gas_read(struct acpi_generic_address *gas)
 {
 	uint32_t ret = 0U;
 
 	if (gas->space_id == SPACE_SYSTEM_MEMORY)
-		ret = mmio_read_word(HPA2HVA(gas->address));
+		ret = mmio_read16(HPA2HVA(gas->address));
 	else
-		ret = io_read_word((uint16_t)gas->address);
+		ret = pio_read16((uint16_t)gas->address);
 
 	return ret;
 }
diff --git a/hypervisor/arch/x86/timer.c b/hypervisor/arch/x86/timer.c
@@ -261,20 +261,20 @@ static uint64_t pit_calibrate_tsc(uint16_t cal_ms_arg)
 	 * Read/Write least significant byte first, mode 0, 16 bits.
 	 */
 
-	io_write_byte(0x30U, 0x43U);
-	io_write_byte(initial_pit_low, 0x40U);	/* Write LSB */
-	io_write_byte(initial_pit_high, 0x40U);		/* Write MSB */
+	pio_write8(0x30U, 0x43U);
+	pio_write8(initial_pit_low, 0x40U);	/* Write LSB */
+	pio_write8(initial_pit_high, 0x40U);		/* Write MSB */
 
 	current_tsc = rdtsc();
 
 	do {
 		/* Port 0x43 ==> Control word write; 0x00 ==> Select
 		 * Counter 0, Counter Latch Command, Mode 0; 16 bits
 		 */
-		io_write_byte(0x00U, 0x43U);
+		pio_write8(0x00U, 0x43U);
 
-		current_pit = io_read_byte(0x40U);	/* Read LSB */
-		current_pit |= io_read_byte(0x40U) << 8U;	/* Read MSB */
+		current_pit = pio_read8(0x40U);	/* Read LSB */
+		current_pit |= pio_read8(0x40U) << 8U;	/* Read MSB */
 		/* Let the counter count down to PIT_TARGET */
 	} while (current_pit > PIT_TARGET);
 
diff --git a/hypervisor/arch/x86/virq.c b/hypervisor/arch/x86/virq.c
@@ -182,11 +182,11 @@ void dump_lapic(void)
 {
 	dev_dbg(ACRN_DBG_INTR,
 		"LAPIC: TIME %08x, init=0x%x cur=0x%x ISR=0x%x IRR=0x%x",
-		mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_LVT_TIMER_REGISTER)),
-		mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_INITIAL_COUNT_REGISTER)),
-		mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_CURRENT_COUNT_REGISTER)),
-		mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_IN_SERVICE_REGISTER_7)),
-		mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_INT_REQUEST_REGISTER_7)));
+		mmio_read32(HPA2HVA(LAPIC_BASE + LAPIC_LVT_TIMER_REGISTER)),
+		mmio_read32(HPA2HVA(LAPIC_BASE + LAPIC_INITIAL_COUNT_REGISTER)),
+		mmio_read32(HPA2HVA(LAPIC_BASE + LAPIC_CURRENT_COUNT_REGISTER)),
+		mmio_read32(HPA2HVA(LAPIC_BASE + LAPIC_IN_SERVICE_REGISTER_7)),
+		mmio_read32(HPA2HVA(LAPIC_BASE + LAPIC_INT_REQUEST_REGISTER_7)));
 }
 
 /* SDM Vol3 -6.15, Table 6-4 - interrupt and exception classes */
diff --git a/hypervisor/arch/x86/vtd.c b/hypervisor/arch/x86/vtd.c
@@ -191,16 +191,16 @@ static void register_hrhd_units(void)
 
 static uint32_t iommu_read32(struct dmar_drhd_rt *dmar_uint, uint32_t offset)
 {
-	return mmio_read_long(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
+	return mmio_read32(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
 }
 
 static uint64_t iommu_read64(struct dmar_drhd_rt *dmar_uint, uint32_t offset)
 {
 	uint64_t value;
 
-	value = mmio_read_long(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4U));
+	value = mmio_read32(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4U));
 	value = value << 32U;
-	value = value | mmio_read_long(HPA2HVA(dmar_uint->drhd->reg_base_addr +
+	value = value | mmio_read32(HPA2HVA(dmar_uint->drhd->reg_base_addr +
 					offset));
 
 	return value;
@@ -209,7 +209,7 @@ static uint64_t iommu_read64(struct dmar_drhd_rt *dmar_uint, uint32_t offset)
 static void iommu_write32(struct dmar_drhd_rt *dmar_uint, uint32_t offset,
 			  uint32_t value)
 {
-	mmio_write_long(value, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
+	mmio_write32(value, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
 }
 
 static void iommu_write64(struct dmar_drhd_rt *dmar_uint, uint32_t offset,
@@ -218,10 +218,10 @@ static void iommu_write64(struct dmar_drhd_rt *dmar_uint, uint32_t offset,
 	uint32_t temp;
 
 	temp = (uint32_t)value;
-	mmio_write_long(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
+	mmio_write32(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
 
 	temp = (uint32_t)(value >> 32U);
-	mmio_write_long(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4U));
+	mmio_write32(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4U));
 }
 
 /* flush cache when root table, context table updated */
diff --git a/hypervisor/boot/dmar_parse.c b/hypervisor/boot/dmar_parse.c
@@ -148,10 +148,10 @@ static uint8_t get_secondary_bus(uint8_t bus, uint8_t dev, uint8_t func)
 {
 	uint32_t data;
 
-	io_write_long(PCI_CONFIG_ACCESS_EN | (bus << 16) | (dev << 11) |
+	pio_write32(PCI_CONFIG_ACCESS_EN | (bus << 16) | (dev << 11) |
 		(func << 8) | 0x18, PCI_CONFIG_ADDRESS);
 
-	data = io_read_long(PCI_CONFIG_DATA);
+	data = pio_read32(PCI_CONFIG_DATA);
 
 	return (data >> 8) & 0xff;
 }
diff --git a/hypervisor/debug/uart16550.c b/hypervisor/debug/uart16550.c
@@ -35,9 +35,9 @@ static spinlock_t uart_tx_lock;
 static inline uint32_t uart16550_read_reg(uint64_t base, uint16_t reg_idx)
 {
 	if (serial_port_mapped) {
-		return io_read_byte((uint16_t)base + reg_idx);
+		return pio_read8((uint16_t)base + reg_idx);
 	} else {
-		return mmio_read_long((void*)((uint32_t*)HPA2HVA(base) + reg_idx));
+		return mmio_read32((void*)((uint32_t*)HPA2HVA(base) + reg_idx));
 	}
 }
 
@@ -48,9 +48,9 @@ static inline void uart16550_write_reg(uint64_t base,
 	uint32_t val, uint16_t reg_idx)
 {
 	if (serial_port_mapped) {
-		io_write_byte((uint8_t)val, (uint16_t)base + reg_idx);
+		pio_write8((uint8_t)val, (uint16_t)base + reg_idx);
 	} else {
-		mmio_write_long(val, (void*)((uint32_t*)HPA2HVA(base) + reg_idx));
+		mmio_write32(val, (void*)((uint32_t*)HPA2HVA(base) + reg_idx));
 	}
 }
 
diff --git a/hypervisor/include/arch/x86/io.h b/hypervisor/include/arch/x86/io.h
@@ -10,13 +10,13 @@
 #include <types.h>
 
 /* Write 1 byte to specified I/O port */
-static inline void io_write_byte(uint8_t value, uint16_t port)
+static inline void pio_write8(uint8_t value, uint16_t port)
 {
 	asm volatile ("outb %0,%1"::"a" (value), "dN"(port));
 }
 
 /* Read 1 byte from specified I/O port */
-static inline uint8_t io_read_byte(uint16_t port)
+static inline uint8_t pio_read8(uint16_t port)
 {
 	uint8_t value;
 
@@ -25,13 +25,13 @@ static inline uint8_t io_read_byte(uint16_t port)
 }
 
 /* Write 2 bytes to specified I/O port */
-static inline void io_write_word(uint16_t value, uint16_t port)
+static inline void pio_write16(uint16_t value, uint16_t port)
 {
 	asm volatile ("outw %0,%1"::"a" (value), "dN"(port));
 }
 
 /* Read 2 bytes from specified I/O port */
-static inline uint16_t io_read_word(uint16_t port)
+static inline uint16_t pio_read16(uint16_t port)
 {
 	uint16_t value;
 
@@ -40,48 +40,48 @@ static inline uint16_t io_read_word(uint16_t port)
 }
 
 /* Write 4 bytes to specified I/O port */
-static inline void io_write_long(uint32_t value, uint16_t port)
+static inline void pio_write32(uint32_t value, uint16_t port)
 {
 	asm volatile ("outl %0,%1"::"a" (value), "dN"(port));
 }
 
 /* Read 4 bytes from specified I/O port */
-static inline uint32_t io_read_long(uint16_t port)
+static inline uint32_t pio_read32(uint16_t port)
 {
 	uint32_t value;
 
 	asm volatile ("inl %1,%0":"=a" (value):"dN"(port));
 	return value;
 }
 
-static inline void io_write(uint32_t v, uint16_t addr, size_t sz)
+static inline void pio_write(uint32_t v, uint16_t addr, size_t sz)
 {
 	if (sz == 1U) {
-		io_write_byte((uint8_t)v, addr);
+		pio_write8((uint8_t)v, addr);
 	} else if (sz == 2U) {
-		io_write_word((uint16_t)v, addr);
+		pio_write16((uint16_t)v, addr);
 	} else {
-		io_write_long(v, addr);
+		pio_write32(v, addr);
 	}
 }
 
-static inline uint32_t io_read(uint16_t addr, size_t sz)
+static inline uint32_t pio_read(uint16_t addr, size_t sz)
 {
 	if (sz == 1U) {
-		return io_read_byte(addr);
+		return pio_read8(addr);
 	}
 	if (sz == 2U) {
-		return io_read_word(addr);
+		return pio_read16(addr);
 	}
-	return io_read_long(addr);
+	return pio_read32(addr);
 }
 
 /** Writes a 32 bit value to a memory mapped IO device.
  *
  *  @param value The 32 bit value to write.
  *  @param addr The memory address to write to.
  */
-static inline void mmio_write_long(uint32_t value, void *addr)
+static inline void mmio_write32(uint32_t value, void *addr)
 {
 	volatile uint32_t *addr32 = (volatile uint32_t *)addr;
 	*addr32 = value;
@@ -92,7 +92,7 @@ static inline void mmio_write_long(uint32_t value, void *addr)
  *  @param value The 16 bit value to write.
  *  @param addr The memory address to write to.
  */
-static inline void mmio_write_word(uint16_t value, void *addr)
+static inline void mmio_write16(uint16_t value, void *addr)
 {
 	volatile uint16_t *addr16 = (volatile uint16_t *)addr;
 	*addr16 = value;
@@ -103,7 +103,7 @@ static inline void mmio_write_word(uint16_t value, void *addr)
  *  @param value The 8 bit value to write.
  *  @param addr The memory address to write to.
  */
-static inline void mmio_write_byte(uint8_t value, void *addr)
+static inline void mmio_write8(uint8_t value, void *addr)
 {
 	volatile uint8_t *addr8 = (volatile uint8_t *)addr;
 	*addr8 = value;
@@ -115,7 +115,7 @@ static inline void mmio_write_byte(uint8_t value, void *addr)
  *
  *  @return The 32 bit value read from the given address.
  */
-static inline uint32_t mmio_read_long(void *addr)
+static inline uint32_t mmio_read32(void *addr)
 {
 	return *((volatile uint32_t *)addr);
 }
@@ -126,7 +126,7 @@ static inline uint32_t mmio_read_long(void *addr)
  *
  *  @return The 16 bit value read from the given address.
  */
-static inline uint16_t mmio_read_word(void *addr)
+static inline uint16_t mmio_read16(void *addr)
 {
 	return *((volatile uint16_t *)addr);
 }
@@ -137,7 +137,7 @@ static inline uint16_t mmio_read_word(void *addr)
  *
  *  @return The 8 bit  value read from the given address.
  */
-static inline uint8_t mmio_read_byte(void *addr)
+static inline uint8_t mmio_read8(void *addr)
 {
 	return *((volatile uint8_t *)addr);
 }
@@ -150,9 +150,9 @@ static inline uint8_t mmio_read_byte(void *addr)
  * @param mask    The mask to apply to the value read.
  * @param value   The 32 bit value to write.
  */
-static inline void setl(void *addr, uint32_t mask, uint32_t value)
+static inline void set32(void *addr, uint32_t mask, uint32_t value)
 {
-	mmio_write_long((mmio_read_long(addr) & ~mask) | value, addr);
+	mmio_write32((mmio_read32(addr) & ~mask) | value, addr);
 }
 
 /** Reads a 16 Bit memory mapped IO register, mask it and write it back into
@@ -162,9 +162,9 @@ static inline void setl(void *addr, uint32_t mask, uint32_t value)
  * @param mask    The mask to apply to the value read.
  * @param value   The 16 bit value to write.
  */
-static inline void setw(void *addr, uint16_t mask, uint16_t value)
+static inline void set16(void *addr, uint16_t mask, uint16_t value)
 {
-	mmio_write_word((mmio_read_word(addr) & ~mask) | value, addr);
+	mmio_write16((mmio_read16(addr) & ~mask) | value, addr);
 }
 
 /** Reads a 8 Bit memory mapped IO register, mask it and write it back into
@@ -174,9 +174,9 @@ static inline void setw(void *addr, uint16_t mask, uint16_t value)
  * @param mask    The mask to apply to the value read.
  * @param value   The 8 bit value to write.
  */
-static inline void setb(void *addr, uint8_t mask, uint8_t value)
+static inline void set8(void *addr, uint8_t mask, uint8_t value)
 {
-	mmio_write_byte((mmio_read_byte(addr) & ~mask) | value, addr);
+	mmio_write8((mmio_read8(addr) & ~mask) | value, addr);
 }
 
 #endif /* _IO_H defined */

Original file line number	Diff line number	Diff line change
`@@ -7,6 +7,6 @@`
`7`	`7`
`8`	`8`	`int warm_reboot(void)`
`9`	`9`	`{`
`10`		`- io_write_byte(0x6, 0xcf9);`
	`10`	`+ pio_write8(0x6, 0xcf9);`
`11`	`11`	`return 0;`
`12`	`12`	`}`
Original file line number	Diff line number	Diff line change
`@@ -137,7 +137,7 @@ static inline uint8_t get_slp_typx(uint32_t pm1_cnt)`
`137`	`137`	`static uint32_t pm1ab_io_read(__unused struct vm_io_handler *hdlr,`
`138`	`138`	`__unused struct vm *vm, uint16_t addr, size_t width)`
`139`	`139`	`{`
`140`		`- uint32_t val = io_read(addr, width);`
	`140`	`+ uint32_t val = pio_read(addr, width);`
`141`	`141`
`142`	`142`	`if (host_enter_s3_success == 0U) {`
`143`	`143`	`/* If host S3 enter failes, we should set BIT_WAK_STS`
`@@ -186,7 +186,7 @@ static void pm1ab_io_write(__unused struct vm_io_handler *hdlr,`
`186`	`186`	`}`
`187`	`187`	`}`
`188`	`188`
`189`		`- io_write(v, addr, width);`
	`189`	`+ pio_write(v, addr, width);`
`190`	`190`	`}`
`191`	`191`
`192`	`192`	`static void`
Original file line number	Diff line number	Diff line change
`@@ -157,8 +157,8 @@ static void _irq_desc_free_vector(uint32_t irq)`
`157`	`157`
`158`	`158`	`static void disable_pic_irq(void)`
`159`	`159`	`{`
`160`		`- io_write_byte(0xffU, 0xA1U);`
`161`		`- io_write_byte(0xffU, 0x21U);`
	`160`	`+ pio_write8(0xffU, 0xA1U);`
	`161`	`+ pio_write8(0xffU, 0x21U);`
`162`	`162`	`}`
`163`	`163`
`164`	`164`	`static bool`
Original file line number	Diff line number	Diff line change
`@@ -143,15 +143,15 @@ static inline uint32_t read_lapic_reg32(uint32_t offset)`
`143`	`143`	`if (offset < 0x20U \|\| offset > 0x3ffU)`
`144`	`144`	`return 0;`
`145`	`145`
`146`		`- return mmio_read_long(lapic_info.xapic.vaddr + offset);`
	`146`	`+ return mmio_read32(lapic_info.xapic.vaddr + offset);`
`147`	`147`	`}`
`148`	`148`
`149`	`149`	`inline void write_lapic_reg32(uint32_t offset, uint32_t value)`
`150`	`150`	`{`
`151`	`151`	`if (offset < 0x20U \|\| offset > 0x3ffU)`
`152`	`152`	`return;`
`153`	`153`
`154`		`- mmio_write_long(value, lapic_info.xapic.vaddr + offset);`
	`154`	`+ mmio_write32(value, lapic_info.xapic.vaddr + offset);`
`155`	`155`	`}`
`156`	`156`
`157`	`157`	`static void clear_lapic_isr(void)`
Original file line number	Diff line number	Diff line change
`@@ -191,16 +191,16 @@ static void register_hrhd_units(void)`
`191`	`191`
`192`	`192`	`static uint32_t iommu_read32(struct dmar_drhd_rt *dmar_uint, uint32_t offset)`
`193`	`193`	`{`
`194`		`- return mmio_read_long(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));`
	`194`	`+ return mmio_read32(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));`
`195`	`195`	`}`
`196`	`196`
`197`	`197`	`static uint64_t iommu_read64(struct dmar_drhd_rt *dmar_uint, uint32_t offset)`
`198`	`198`	`{`
`199`	`199`	`uint64_t value;`
`200`	`200`
`201`		`- value = mmio_read_long(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4U));`
	`201`	`+ value = mmio_read32(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4U));`
`202`	`202`	`value = value << 32U;`
`203`		`- value = value \| mmio_read_long(HPA2HVA(dmar_uint->drhd->reg_base_addr +`
	`203`	`+ value = value \| mmio_read32(HPA2HVA(dmar_uint->drhd->reg_base_addr +`
`204`	`204`	`offset));`
`205`	`205`
`206`	`206`	`return value;`
`@@ -209,7 +209,7 @@ static uint64_t iommu_read64(struct dmar_drhd_rt *dmar_uint, uint32_t offset)`
`209`	`209`	`static void iommu_write32(struct dmar_drhd_rt *dmar_uint, uint32_t offset,`
`210`	`210`	`uint32_t value)`
`211`	`211`	`{`
`212`		`- mmio_write_long(value, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));`
	`212`	`+ mmio_write32(value, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));`
`213`	`213`	`}`
`214`	`214`
`215`	`215`	`static void iommu_write64(struct dmar_drhd_rt *dmar_uint, uint32_t offset,`
`@@ -218,10 +218,10 @@ static void iommu_write64(struct dmar_drhd_rt *dmar_uint, uint32_t offset,`
`218`	`218`	`uint32_t temp;`
`219`	`219`
`220`	`220`	`temp = (uint32_t)value;`
`221`		`- mmio_write_long(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));`
	`221`	`+ mmio_write32(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));`
`222`	`222`
`223`	`223`	`temp = (uint32_t)(value >> 32U);`
`224`		`- mmio_write_long(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4U));`
	`224`	`+ mmio_write32(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4U));`
`225`	`225`	`}`
`226`	`226`
`227`	`227`	`/* flush cache when root table, context table updated */`
Original file line number	Diff line number	Diff line change
`@@ -148,10 +148,10 @@ static uint8_t get_secondary_bus(uint8_t bus, uint8_t dev, uint8_t func)`
`148`	`148`	`{`
`149`	`149`	`uint32_t data;`
`150`	`150`
`151`		`- io_write_long(PCI_CONFIG_ACCESS_EN \| (bus << 16) \| (dev << 11) \|`
	`151`	`+ pio_write32(PCI_CONFIG_ACCESS_EN \| (bus << 16) \| (dev << 11) \|`
`152`	`152`	`(func << 8) \| 0x18, PCI_CONFIG_ADDRESS);`
`153`	`153`
`154`		`- data = io_read_long(PCI_CONFIG_DATA);`
	`154`	`+ data = pio_read32(PCI_CONFIG_DATA);`
`155`	`155`
`156`	`156`	`return (data >> 8) & 0xff;`
`157`	`157`	`}`