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#define VAPIC_FEATURE_POST_INTR (1U << 4U)
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#define VAPIC_FEATURE_VX2APIC_MODE (1U << 5U)
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- static struct vmx_capability {
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- uint32_t ept ;
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- uint32_t vpid ;
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- } vmx_caps ;
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-
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struct cpu_capability {
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uint8_t apicv_features ;
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uint8_t ept_features ;
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- };
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- static struct cpu_capability cpu_caps ;
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+
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+ uint32_t vmx_ept ;
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+ uint32_t vmx_vpid ;
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+ } cpu_caps ;
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struct cpuinfo_x86 boot_cpu_data ;
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@@ -261,10 +258,21 @@ static void apicv_cap_detect(void)
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cpu_caps .apicv_features = features ;
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}
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+ static void vmx_mmu_cap_detect (void )
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+ {
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+ uint64_t val ;
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+
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+ /* Read the MSR register of EPT and VPID Capability - SDM A.10 */
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+ val = msr_read (MSR_IA32_VMX_EPT_VPID_CAP );
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+ cpu_caps .vmx_ept = (uint32_t ) val ;
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+ cpu_caps .vmx_vpid = (uint32_t ) (val >> 32U );
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+ }
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+
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void cpu_cap_detect (void )
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{
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apicv_cap_detect ();
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ept_cap_detect ();
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+ vmx_mmu_cap_detect ();
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}
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bool is_ept_supported (void )
@@ -287,6 +295,16 @@ bool is_apicv_posted_intr_supported(void)
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return ((cpu_caps .apicv_features & VAPIC_FEATURE_POST_INTR ) != 0U );
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}
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+ bool cpu_has_vmx_ept_cap (uint32_t bit_mask )
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+ {
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+ return ((cpu_caps .vmx_ept & bit_mask ) != 0U );
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+ }
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+
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+ bool cpu_has_vmx_vpid_cap (uint32_t bit_mask )
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+ {
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+ return ((cpu_caps .vmx_vpid & bit_mask ) != 0U );
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+ }
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+
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void get_cpu_name (void )
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{
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cpuid (CPUID_EXTEND_FUNCTION_2 ,
@@ -366,25 +384,8 @@ static inline bool cpu_has_vmx_unrestricted_guest_cap(void)
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!= 0UL );
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}
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- bool cpu_has_vmx_ept_cap (uint32_t bit_mask )
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- {
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- return ((vmx_caps .ept & bit_mask ) != 0U );
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- }
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-
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- bool cpu_has_vmx_vpid_cap (uint32_t bit_mask )
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- {
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- return ((vmx_caps .vpid & bit_mask ) != 0U );
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- }
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-
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static int32_t check_vmx_mmu_cap (void )
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{
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- uint64_t val ;
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-
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- /* Read the MSR register of EPT and VPID Capability - SDM A.10 */
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- val = msr_read (MSR_IA32_VMX_EPT_VPID_CAP );
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- vmx_caps .ept = (uint32_t ) val ;
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- vmx_caps .vpid = (uint32_t ) (val >> 32U );
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-
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if (!cpu_has_vmx_ept_cap (VMX_EPT_INVEPT )) {
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pr_fatal ("%s, invept not supported\n" , __func__ );
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return - ENODEV ;
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