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JasonChenCJwenlingz
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modulization: combine vmx_caps into cpu_caps
in cpu_caps.c, the vmx_caps & cpu_caps can be combined. Changes to be committed: modified: arch/x86/cpu_caps.c Tracked-On: #1842 Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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+25
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hypervisor/arch/x86/cpu_caps.c

Lines changed: 25 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -26,16 +26,13 @@
2626
#define VAPIC_FEATURE_POST_INTR (1U << 4U)
2727
#define VAPIC_FEATURE_VX2APIC_MODE (1U << 5U)
2828

29-
static struct vmx_capability {
30-
uint32_t ept;
31-
uint32_t vpid;
32-
} vmx_caps;
33-
3429
struct cpu_capability {
3530
uint8_t apicv_features;
3631
uint8_t ept_features;
37-
};
38-
static struct cpu_capability cpu_caps;
32+
33+
uint32_t vmx_ept;
34+
uint32_t vmx_vpid;
35+
} cpu_caps;
3936

4037
struct cpuinfo_x86 boot_cpu_data;
4138

@@ -261,10 +258,21 @@ static void apicv_cap_detect(void)
261258
cpu_caps.apicv_features = features;
262259
}
263260

261+
static void vmx_mmu_cap_detect(void)
262+
{
263+
uint64_t val;
264+
265+
/* Read the MSR register of EPT and VPID Capability - SDM A.10 */
266+
val = msr_read(MSR_IA32_VMX_EPT_VPID_CAP);
267+
cpu_caps.vmx_ept = (uint32_t) val;
268+
cpu_caps.vmx_vpid = (uint32_t) (val >> 32U);
269+
}
270+
264271
void cpu_cap_detect(void)
265272
{
266273
apicv_cap_detect();
267274
ept_cap_detect();
275+
vmx_mmu_cap_detect();
268276
}
269277

270278
bool is_ept_supported(void)
@@ -287,6 +295,16 @@ bool is_apicv_posted_intr_supported(void)
287295
return ((cpu_caps.apicv_features & VAPIC_FEATURE_POST_INTR) != 0U);
288296
}
289297

298+
bool cpu_has_vmx_ept_cap(uint32_t bit_mask)
299+
{
300+
return ((cpu_caps.vmx_ept & bit_mask) != 0U);
301+
}
302+
303+
bool cpu_has_vmx_vpid_cap(uint32_t bit_mask)
304+
{
305+
return ((cpu_caps.vmx_vpid & bit_mask) != 0U);
306+
}
307+
290308
void get_cpu_name(void)
291309
{
292310
cpuid(CPUID_EXTEND_FUNCTION_2,
@@ -366,25 +384,8 @@ static inline bool cpu_has_vmx_unrestricted_guest_cap(void)
366384
!= 0UL);
367385
}
368386

369-
bool cpu_has_vmx_ept_cap(uint32_t bit_mask)
370-
{
371-
return ((vmx_caps.ept & bit_mask) != 0U);
372-
}
373-
374-
bool cpu_has_vmx_vpid_cap(uint32_t bit_mask)
375-
{
376-
return ((vmx_caps.vpid & bit_mask) != 0U);
377-
}
378-
379387
static int32_t check_vmx_mmu_cap(void)
380388
{
381-
uint64_t val;
382-
383-
/* Read the MSR register of EPT and VPID Capability - SDM A.10 */
384-
val = msr_read(MSR_IA32_VMX_EPT_VPID_CAP);
385-
vmx_caps.ept = (uint32_t) val;
386-
vmx_caps.vpid = (uint32_t) (val >> 32U);
387-
388389
if (!cpu_has_vmx_ept_cap(VMX_EPT_INVEPT)) {
389390
pr_fatal("%s, invept not supported\n", __func__);
390391
return -ENODEV;

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