DM: set cs_limit from DM side for UOS

For CS of UOS, we would like to pass all related info (cs attribute,
limit, base) from DM.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <Eddie.dong@intel.com>

Author: fyin1

devicemodel/core/sw_load_bzimage.c

@@ -344,6 +344,7 @@ acrn_sw_load_bzimage(struct vmctx *ctx)
 
 	ctx->bsp_regs.vcpu_regs.cs_sel = 0x10U;
 	ctx->bsp_regs.vcpu_regs.cs_ar = 0xC09BU;
+	ctx->bsp_regs.vcpu_regs.cs_limit = 0xFFFFFFFFU;
 
 	ctx->bsp_regs.vcpu_regs.ds_sel = 0x18U;
 	ctx->bsp_regs.vcpu_regs.ss_sel = 0x18U;

devicemodel/core/sw_load_elf.c

@@ -283,6 +283,7 @@ acrn_sw_load_elf(struct vmctx *ctx)
 
 	ctx->bsp_regs.vcpu_regs.cs_ar = 0xCF9BU;
 	ctx->bsp_regs.vcpu_regs.cs_sel = 0x8U;
+	ctx->bsp_regs.vcpu_regs.cs_limit = 0xFFFFFFFFU;
 
 	ctx->bsp_regs.vcpu_regs.ds_sel = 0x10U;
 	ctx->bsp_regs.vcpu_regs.ss_sel = 0x10U;

devicemodel/core/sw_load_vsbl.c

@@ -307,6 +307,7 @@ acrn_sw_load_vsbl(struct vmctx *ctx)
 	ctx->bsp_regs.vcpu_regs.cr0 = 0x30U;
 	ctx->bsp_regs.vcpu_regs.cs_ar = 0x009FU;
 	ctx->bsp_regs.vcpu_regs.cs_sel = 0xF000U;
+	ctx->bsp_regs.vcpu_regs.cs_limit = 0xFFFFU;
 	ctx->bsp_regs.vcpu_regs.cs_base = (VSBL_TOP(ctx) - 16) &0xFFFF0000UL;
 	ctx->bsp_regs.vcpu_regs.rip = (VSBL_TOP(ctx) - 16) & 0xFFFFUL;
 	ctx->bsp_regs.vcpu_regs.gprs.rsi = CONFIGPAGE_OFF(ctx);

devicemodel/include/public/acrn_common.h

@@ -309,7 +309,8 @@ struct acrn_vcpu_regs {
 	uint64_t        reserved_64[4];
 
 	uint32_t        cs_ar;
-	uint32_t        reserved_32[4];
+	uint32_t        cs_limit;
+	uint32_t        reserved_32[3];
 
 	/* don't change the order of following sel */
 	uint16_t        cs_sel;