HV: vioapic: cleaning up integral-type-related violations

This patch cleans up the integral-type-related violations after the access
pattern to RTEs is unified. Major changes include:

    1. vioapic_mmio_read(), vioapic_mmio_write() and vioapic_mmio_rw() assumes
       the size of the register to be accessed is always 4, which is checked in
       vioapic_mmio_access_handler(). Thus they no longer takes the unused
       ''size'' parameter.

    2. Typical integral-type-related violation fixes including 'U' suffixes,
       type of local variables, conversion specification in format strings, etc.

v1 -> v2:

    * Drop duplicated definitions to IOAPIC register offsets.
    * Drop the ''size'' parameter of vioapic_mmio_[read|write] and
      vioapic_mmio_rw since vioapic_mmio_access_handler() ensures that size is
      always 4.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

Author: junjiemao1

hypervisor/arch/x86/guest/vioapic.c

@@ -32,15 +32,11 @@
 
 #include <hypervisor.h>
 
-#define	IOREGSEL	0x00
-#define	IOWIN		0x10
-#define	IOEOI		0x40
-
 #define REDIR_ENTRIES_HW	120U /* SOS align with native ioapic */
 #define	RTBL_RO_BITS	(uint32_t)(IOAPIC_RTE_REM_IRR | IOAPIC_RTE_DELIVS)
 #define NEED_TMR_UPDATE (~(IOAPIC_RTE_INTMASK | IOAPIC_RTE_INTPOL))
 
-#define ACRN_DBG_IOAPIC	6
+#define ACRN_DBG_IOAPIC	6U
 
 struct vioapic {
 	struct vm	*vm;
@@ -432,34 +428,34 @@ vioapic_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
 	}
 }
 
-static int
+static void
 vioapic_mmio_rw(struct vioapic *vioapic, uint64_t gpa,
-		uint64_t *data, int size, bool doread)
+		uint32_t *data, bool doread)
 {
-	uint64_t offset;
+	uint32_t offset;
 
-	offset = gpa - VIOAPIC_BASE;
+	offset = (uint32_t)(gpa - VIOAPIC_BASE);
 
 	/*
 	 * The IOAPIC specification allows 32-bit wide accesses to the
-	 * IOREGSEL (offset 0) and IOWIN (offset 16) registers.
+	 * IOAPIC_REGSEL (offset 0) and IOAPIC_WINDOW (offset 16) registers.
 	 */
-	if (size != 4 || (offset != IOREGSEL && offset != IOWIN &&
-			offset != IOEOI)) {
+	if (offset != IOAPIC_REGSEL &&
+		offset != IOAPIC_WINDOW &&
+		offset != IOAPIC_EOIR) {
 		if (doread) {
-			*data = 0UL;
+			*data = 0U;
 		}
-		return 0;
 	}
 
 	VIOAPIC_LOCK(vioapic);
-	if (offset == IOREGSEL) {
+	if (offset == IOAPIC_REGSEL) {
 		if (doread) {
 			*data = vioapic->ioregsel;
 		} else {
 			vioapic->ioregsel = *data;
 		}
-	} else if (offset == IOEOI) {
+	} else if (offset == IOAPIC_EOIR) {
 		/* only need to handle write operation */
 		if (!doread) {
 			vioapic_write_eoi(vioapic, *data);
@@ -473,32 +469,24 @@ vioapic_mmio_rw(struct vioapic *vioapic, uint64_t gpa,
 		}
 	}
 	VIOAPIC_UNLOCK(vioapic);
-
-	return 0;
 }
 
-int
-vioapic_mmio_read(void *vm, uint64_t gpa, uint64_t *rval,
-		int size)
+void
+vioapic_mmio_read(struct vm *vm, uint64_t gpa, uint32_t *rval)
 {
-	int error;
 	struct vioapic *vioapic;
 
 	vioapic = vm_ioapic(vm);
-	error = vioapic_mmio_rw(vioapic, gpa, rval, size, true);
-	return error;
+	vioapic_mmio_rw(vioapic, gpa, rval, true);
 }
 
-int
-vioapic_mmio_write(void *vm, uint64_t gpa, uint64_t wval,
-		int size)
+void
+vioapic_mmio_write(struct vm *vm, uint64_t gpa, uint32_t wval)
 {
-	int error;
 	struct vioapic *vioapic;
 
 	vioapic = vm_ioapic(vm);
-	error = vioapic_mmio_rw(vioapic, gpa, &wval, size, false);
-	return error;
+	vioapic_mmio_rw(vioapic, gpa, &wval, false);
 }
 
 void
@@ -569,7 +557,7 @@ vioapic_init(struct vm *vm)
 {
 	struct vioapic *vioapic;
 
-	vioapic = calloc(1, sizeof(struct vioapic));
+	vioapic = calloc(1U, sizeof(struct vioapic));
 	ASSERT(vioapic != NULL, "");
 
 	vioapic->vm = vm;
@@ -581,7 +569,7 @@ vioapic_init(struct vm *vm)
 			vioapic_mmio_access_handler,
 			(uint64_t)VIOAPIC_BASE,
 			(uint64_t)VIOAPIC_BASE + VIOAPIC_SIZE,
-			(void *) 0);
+			NULL);
 
 	return vioapic;
 }
@@ -613,23 +601,26 @@ int vioapic_mmio_access_handler(struct vcpu *vcpu, struct mem_io *mmio,
 	int ret = 0;
 
 	/* Note all RW to IOAPIC are 32-Bit in size */
-	ASSERT(mmio->access_size == 4U,
-			"All RW to LAPIC must be 32-bits in size");
-
-	if (mmio->read_write == HV_MEM_IO_READ) {
-		ret = vioapic_mmio_read(vm,
-				gpa,
-				&mmio->value,
-				mmio->access_size);
-		mmio->mmio_status = MMIO_TRANS_VALID;
-
-	} else if (mmio->read_write == HV_MEM_IO_WRITE) {
-		ret = vioapic_mmio_write(vm,
-				gpa,
-				mmio->value,
-				mmio->access_size);
-
-		mmio->mmio_status = MMIO_TRANS_VALID;
+	if (mmio->access_size == 4U) {
+		uint32_t data = mmio->value;
+
+		if (mmio->read_write == HV_MEM_IO_READ) {
+			vioapic_mmio_read(vm,
+					gpa,
+					&data);
+			mmio->value = (uint64_t)data;
+			mmio->mmio_status = MMIO_TRANS_VALID;
+
+		} else if (mmio->read_write == HV_MEM_IO_WRITE) {
+			vioapic_mmio_write(vm,
+					gpa,
+					data);
+
+			mmio->mmio_status = MMIO_TRANS_VALID;
+		}
+	} else {
+		pr_err("All RW to IOAPIC must be 32-bits in size");
+		ret = -EINVAL;
 	}
 
 	return ret;

hypervisor/arch/x86/ioapic.c

@@ -6,11 +6,7 @@
 
 #include <hypervisor.h>
 
-/* Register offsets */
-#define IOAPIC_REGSEL_OFFSET   0
-#define IOAPIC_WINSWL_OFFSET   0x10
-
-#define IOAPIC_MAX_PIN          240U
+#define	IOAPIC_MAX_PIN		240U
 #define IOAPIC_INVALID_PIN      0xffU
 
 struct gsi_table {
@@ -103,9 +99,9 @@ ioapic_read_reg32(const void *ioapic_base, const uint32_t offset)
 	spinlock_irqsave_obtain(&ioapic_lock);
 
 	/* Write IOREGSEL */
-	mmio_write_long(offset, (void *)ioapic_base + IOAPIC_REGSEL_OFFSET);
+	mmio_write_long(offset, (void *)ioapic_base + IOAPIC_REGSEL);
 	/* Read  IOWIN */
-	v = mmio_read_long((void *)ioapic_base + IOAPIC_WINSWL_OFFSET);
+	v = mmio_read_long((void *)ioapic_base + IOAPIC_WINDOW);
 
 	spinlock_irqrestore_release(&ioapic_lock);
 	return v;
@@ -120,9 +116,9 @@ ioapic_write_reg32(const void *ioapic_base,
 	spinlock_irqsave_obtain(&ioapic_lock);
 
 	/* Write IOREGSEL */
-	mmio_write_long(offset, (void *)ioapic_base + IOAPIC_REGSEL_OFFSET);
+	mmio_write_long(offset, (void *)ioapic_base + IOAPIC_REGSEL);
 	/* Write IOWIN */
-	mmio_write_long(value, (void *)ioapic_base + IOAPIC_WINSWL_OFFSET);
+	mmio_write_long(value, (void *)ioapic_base + IOAPIC_WINDOW);
 
 	spinlock_irqrestore_release(&ioapic_lock);
 }

hypervisor/include/arch/x86/apicreg.h

@@ -449,6 +449,7 @@ union ioapic_rte {
 #define DEFAULT_IO_APIC_BASE	0xfec00000UL
 
 /* window register offset */
+#define IOAPIC_REGSEL		0x00U
 #define IOAPIC_WINDOW		0x10U
 #define IOAPIC_EOIR		0x40U
 

hypervisor/include/arch/x86/guest/vioapic.h

@@ -46,10 +46,8 @@ int	vioapic_deassert_irq(struct vm *vm, uint32_t irq);
 int	vioapic_pulse_irq(struct vm *vm, uint32_t irq);
 void	vioapic_update_tmr(struct vcpu *vcpu);
 
-int	vioapic_mmio_write(void *vm, uint64_t gpa,
-	    uint64_t wval, int size);
-int	vioapic_mmio_read(void *vm, uint64_t gpa,
-	    uint64_t *rval, int size);
+void	vioapic_mmio_write(struct vm *vm, uint64_t gpa, uint32_t wval);
+void	vioapic_mmio_read(struct vm *vm, uint64_t gpa, uint32_t *rval);
 
 uint8_t	vioapic_pincount(struct vm *vm);
 void	vioapic_process_eoi(struct vm *vm, uint32_t vector);