Skip to content

Commit 6d5456a

Browse files
Sainath Grandhiwenlingz
Sainath Grandhi
authored and
wenlingz
committed
hv: Bit Representation for IOAPIC RTE
As we enable Interrupt Remapping, bit positions in IOAPIC RTEs have a different syntax for programming. ACRN should handle original format for vIOAPIC as well IR representation for physical IOAPIC. This patch adds bit granularity IOAPIC RTE. Tracked-On: #2407 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
1 parent 7d57eb0 commit 6d5456a

File tree

8 files changed

+158
-175
lines changed

8 files changed

+158
-175
lines changed

‎hypervisor/arch/x86/assign.c

Lines changed: 29 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -54,9 +54,9 @@ ptirq_lookup_entry_by_vpin(const struct acrn_vm *vm, uint32_t virt_pin, bool pic
5454
return entry;
5555
}
5656

57-
static uint64_t calculate_logical_dest_mask(uint64_t pdmask)
57+
static uint32_t calculate_logical_dest_mask(uint64_t pdmask)
5858
{
59-
uint64_t dest_mask = 0UL;
59+
uint32_t dest_mask = 0UL;
6060
uint64_t pcpu_mask = pdmask;
6161
uint16_t pcpu_id;
6262

@@ -72,8 +72,8 @@ static uint64_t calculate_logical_dest_mask(uint64_t pdmask)
7272
static void ptirq_build_physical_msi(struct acrn_vm *vm, struct ptirq_msi_info *info,
7373
uint32_t vector)
7474
{
75-
uint64_t vdmask, pdmask, dest_mask;
76-
uint32_t dest, delmode;
75+
uint64_t vdmask, pdmask;
76+
uint32_t dest, delmode, dest_mask;
7777
bool phys;
7878

7979
/* get physical destination cpu mask */
@@ -114,16 +114,16 @@ ptirq_build_physical_rte(struct acrn_vm *vm, struct ptirq_remapping_info *entry)
114114
union source_id *virt_sid = &entry->virt_sid;
115115

116116
if (virt_sid->intx_id.src == PTDEV_VPIN_IOAPIC) {
117-
uint64_t vdmask, pdmask, delmode, dest_mask, vector;
118-
uint32_t dest;
117+
uint64_t vdmask, pdmask;
118+
uint32_t dest, delmode, dest_mask, vector;
119119
union ioapic_rte virt_rte;
120120
bool phys;
121121

122122
vioapic_get_rte(vm, virt_sid->intx_id.pin, &virt_rte);
123123
rte = virt_rte;
124124

125125
/* init polarity & pin state */
126-
if ((rte.full & IOAPIC_RTE_INTPOL) != 0UL) {
126+
if (rte.bits.intr_polarity == IOAPIC_RTE_INTPOL_ALO) {
127127
if (entry->polarity == 0U) {
128128
vioapic_set_irqline_nolock(vm, virt_sid->intx_id.pin, GSI_SET_HIGH);
129129
}
@@ -136,27 +136,27 @@ ptirq_build_physical_rte(struct acrn_vm *vm, struct ptirq_remapping_info *entry)
136136
}
137137

138138
/* physical destination cpu mask */
139-
phys = ((virt_rte.full & IOAPIC_RTE_DESTMOD) == IOAPIC_RTE_DESTPHY);
140-
dest = (uint32_t)(virt_rte.full >> IOAPIC_RTE_DEST_SHIFT);
139+
phys = (virt_rte.bits.dest_mode == IOAPIC_RTE_DESTMODE_PHY);
140+
dest = (uint32_t)virt_rte.bits.dest_field;
141141
vlapic_calcdest(vm, &vdmask, dest, phys, false);
142142
pdmask = vcpumask2pcpumask(vm, vdmask);
143143

144144
/* physical delivery mode */
145-
delmode = virt_rte.full & IOAPIC_RTE_DELMOD;
146-
if ((delmode != IOAPIC_RTE_DELFIXED) &&
147-
(delmode != IOAPIC_RTE_DELLOPRI)) {
148-
delmode = IOAPIC_RTE_DELLOPRI;
145+
delmode = virt_rte.bits.delivery_mode;
146+
if ((delmode != IOAPIC_RTE_DELMODE_FIXED) &&
147+
(delmode != IOAPIC_RTE_DELMODE_LOPRI)) {
148+
delmode = IOAPIC_RTE_DELMODE_LOPRI;
149149
}
150150

151151
/* update physical delivery mode, dest mode(logical) & vector */
152-
vector = (uint64_t)irq_to_vector(phys_irq);
153-
rte.full &= ~(IOAPIC_RTE_DESTMOD | IOAPIC_RTE_DELMOD | IOAPIC_RTE_INTVEC);
154-
rte.full |= IOAPIC_RTE_DESTLOG | delmode | vector;
152+
vector = irq_to_vector(phys_irq);
153+
rte.bits.dest_mode = IOAPIC_RTE_DESTMODE_LOGICAL;
154+
rte.bits.delivery_mode = delmode;
155+
rte.bits.vector = vector;
155156

156157
dest_mask = calculate_logical_dest_mask(pdmask);
157158
/* update physical dest field */
158-
rte.full &= ~IOAPIC_RTE_DEST_MASK;
159-
rte.full |= dest_mask << IOAPIC_RTE_DEST_SHIFT;
159+
rte.bits.dest_field = dest_mask;
160160

161161
dev_dbg(ACRN_DBG_IRQ, "IOAPIC RTE = 0x%x:%x(V) -> 0x%x:%x(P)",
162162
virt_rte.u.hi_32, virt_rte.u.lo_32,
@@ -167,10 +167,11 @@ ptirq_build_physical_rte(struct acrn_vm *vm, struct ptirq_remapping_info *entry)
167167

168168
/* just update trigger mode */
169169
ioapic_get_rte(phys_irq, &phys_rte);
170-
rte.full = phys_rte.full & (~IOAPIC_RTE_TRGRMOD);
171-
vpic_get_irqline_trigger_mode(vm, virt_sid->intx_id.pin, &trigger);
170+
rte = phys_rte;
171+
rte.bits.trigger_mode = IOAPIC_RTE_TRGRMODE_EDGE;
172+
vpic_get_irqline_trigger_mode(vm, (uint32_t)virt_sid->intx_id.pin, &trigger);
172173
if (trigger == LEVEL_TRIGGER) {
173-
rte.full |= IOAPIC_RTE_TRGRLVL;
174+
rte.bits.trigger_mode = IOAPIC_RTE_TRGRMODE_LEVEL;
174175
}
175176

176177
dev_dbg(ACRN_DBG_IRQ, "IOAPIC RTE = 0x%x:%x(P) -> 0x%x:%x(P)",
@@ -367,8 +368,8 @@ static void ptirq_handle_intx(struct acrn_vm *vm,
367368
bool trigger_lvl = false;
368369

369370
/* VPIN_IOAPIC src means we have vioapic enabled */
370-
vioapic_get_rte(vm, virt_sid->intx_id.pin, &rte);
371-
if ((rte.full & IOAPIC_RTE_TRGRMOD) == IOAPIC_RTE_TRGRLVL) {
371+
vioapic_get_rte(vm, (uint32_t)virt_sid->intx_id.pin, &rte);
372+
if (rte.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_LEVEL) {
372373
trigger_lvl = true;
373374
}
374375

@@ -557,27 +558,27 @@ static void activate_physical_ioapic(struct acrn_vm *vm,
557558
{
558559
union ioapic_rte rte;
559560
uint32_t phys_irq = entry->allocated_pirq;
560-
uint32_t intr_mask;
561+
uint64_t intr_mask;
561562
bool is_lvl_trigger = false;
562563

563564
/* disable interrupt */
564565
ioapic_gsi_mask_irq(phys_irq);
565566

566567
/* build physical IOAPIC RTE */
567568
rte = ptirq_build_physical_rte(vm, entry);
568-
intr_mask = (uint32_t)(rte.full & IOAPIC_RTE_INTMASK);
569+
intr_mask = rte.bits.intr_mask;
569570

570571
/* update irq trigger mode according to info in guest */
571-
if ((rte.full & IOAPIC_RTE_TRGRMOD) == IOAPIC_RTE_TRGRLVL) {
572+
if (rte.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_LEVEL) {
572573
is_lvl_trigger = true;
573574
}
574575
set_irq_trigger_mode(phys_irq, is_lvl_trigger);
575576

576577
/* set rte entry when masked */
577-
rte.full |= IOAPIC_RTE_INTMSET;
578+
rte.bits.intr_mask = IOAPIC_RTE_MASK_SET;
578579
ioapic_set_rte(phys_irq, rte);
579580

580-
if (intr_mask == IOAPIC_RTE_INTMCLR) {
581+
if (intr_mask == IOAPIC_RTE_MASK_CLR) {
581582
ioapic_gsi_unmask_irq(phys_irq);
582583
}
583584
}

‎hypervisor/arch/x86/guest/vlapic.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1806,13 +1806,13 @@ vlapic_deliver_intr(struct acrn_vm *vm, bool level, uint32_t dest, bool phys,
18061806
uint64_t dmask;
18071807
struct acrn_vcpu *target_vcpu;
18081808

1809-
if ((delmode != IOAPIC_RTE_DELFIXED) &&
1810-
(delmode != IOAPIC_RTE_DELLOPRI) &&
1811-
(delmode != IOAPIC_RTE_DELEXINT)) {
1809+
if ((delmode != IOAPIC_RTE_DELMODE_FIXED) &&
1810+
(delmode != IOAPIC_RTE_DELMODE_LOPRI) &&
1811+
(delmode != IOAPIC_RTE_DELMODE_EXINT)) {
18121812
dev_dbg(ACRN_DBG_LAPIC,
18131813
"vlapic intr invalid delmode %#x", delmode);
18141814
} else {
1815-
lowprio = (delmode == IOAPIC_RTE_DELLOPRI) || rh;
1815+
lowprio = (delmode == IOAPIC_RTE_DELMODE_LOPRI) || rh;
18161816

18171817
/*
18181818
* We don't provide any virtual interrupt redirection hardware so
@@ -1829,7 +1829,7 @@ vlapic_deliver_intr(struct acrn_vm *vm, bool level, uint32_t dest, bool phys,
18291829
/* only make request when vlapic enabled */
18301830
vlapic = vcpu_vlapic(target_vcpu);
18311831
if (vlapic_enabled(vlapic)) {
1832-
if (delmode == IOAPIC_RTE_DELEXINT) {
1832+
if (delmode == IOAPIC_RTE_DELMODE_EXINT) {
18331833
vcpu_inject_extint(target_vcpu);
18341834
} else {
18351835
vlapic_set_intr(target_vcpu, vec, level);

‎hypervisor/arch/x86/ioapic.c

Lines changed: 37 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -45,23 +45,23 @@ static const uint32_t legacy_irq_to_pin[NR_LEGACY_IRQ] = {
4545
15U, /* IRQ15*/
4646
};
4747

48-
static const uint64_t legacy_irq_trigger_mode[NR_LEGACY_IRQ] = {
49-
IOAPIC_RTE_TRGREDG, /* IRQ0*/
50-
IOAPIC_RTE_TRGREDG, /* IRQ1*/
51-
IOAPIC_RTE_TRGREDG, /* IRQ2*/
52-
IOAPIC_RTE_TRGREDG, /* IRQ3*/
53-
IOAPIC_RTE_TRGREDG, /* IRQ4*/
54-
IOAPIC_RTE_TRGREDG, /* IRQ5*/
55-
IOAPIC_RTE_TRGREDG, /* IRQ6*/
56-
IOAPIC_RTE_TRGREDG, /* IRQ7*/
57-
IOAPIC_RTE_TRGREDG, /* IRQ8*/
58-
IOAPIC_RTE_TRGRLVL, /* IRQ9*/
59-
IOAPIC_RTE_TRGREDG, /* IRQ10*/
60-
IOAPIC_RTE_TRGREDG, /* IRQ11*/
61-
IOAPIC_RTE_TRGREDG, /* IRQ12*/
62-
IOAPIC_RTE_TRGREDG, /* IRQ13*/
63-
IOAPIC_RTE_TRGREDG, /* IRQ14*/
64-
IOAPIC_RTE_TRGREDG, /* IRQ15*/
48+
static const uint32_t legacy_irq_trigger_mode[NR_LEGACY_IRQ] = {
49+
IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ0*/
50+
IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ1*/
51+
IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ2*/
52+
IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ3*/
53+
IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ4*/
54+
IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ5*/
55+
IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ6*/
56+
IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ7*/
57+
IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ8*/
58+
IOAPIC_RTE_TRGRMODE_LEVEL, /* IRQ9*/
59+
IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ10*/
60+
IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ11*/
61+
IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ12*/
62+
IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ13*/
63+
IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ14*/
64+
IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ15*/
6565
};
6666

6767
static const uint32_t pic_ioapic_pin_map[NR_LEGACY_PIN] = {
@@ -184,17 +184,18 @@ create_rte_for_legacy_irq(uint32_t irq, uint32_t vr)
184184
* before we have ACPI table parsing in HV we use common hardcode
185185
*/
186186

187-
rte.full = IOAPIC_RTE_INTMSET;
188-
rte.full |= legacy_irq_trigger_mode[irq];
189-
rte.full |= DEFAULT_DEST_MODE;
190-
rte.full |= DEFAULT_DELIVERY_MODE;
191-
rte.full |= (IOAPIC_RTE_INTVEC & (uint64_t)vr);
187+
rte.full = 0UL;
188+
rte.bits.intr_mask = IOAPIC_RTE_MASK_SET;
189+
rte.bits.trigger_mode = legacy_irq_trigger_mode[irq];
190+
rte.bits.dest_mode = DEFAULT_DEST_MODE;
191+
rte.bits.delivery_mode = DEFAULT_DELIVERY_MODE;
192+
rte.bits.vector = vr;
192193

193194
/* Fixed to active high */
194-
rte.full |= IOAPIC_RTE_INTAHI;
195+
rte.bits.intr_polarity = IOAPIC_RTE_INTPOL_AHI;
195196

196197
/* Dest field: legacy irq fixed to CPU0 */
197-
rte.full |= (1UL << IOAPIC_RTE_DEST_SHIFT);
198+
rte.bits.dest_field = 1U;
198199

199200
return rte;
200201
}
@@ -204,21 +205,23 @@ create_rte_for_gsi_irq(uint32_t irq, uint32_t vr)
204205
{
205206
union ioapic_rte rte;
206207

208+
rte.full = 0UL;
209+
207210
if (irq < NR_LEGACY_IRQ) {
208211
rte = create_rte_for_legacy_irq(irq, vr);
209212
} else {
210213
/* irq default masked, level trig */
211-
rte.full = IOAPIC_RTE_INTMSET;
212-
rte.full |= IOAPIC_RTE_TRGRLVL;
213-
rte.full |= DEFAULT_DEST_MODE;
214-
rte.full |= DEFAULT_DELIVERY_MODE;
215-
rte.full |= (IOAPIC_RTE_INTVEC & (uint64_t)vr);
214+
rte.bits.intr_mask = IOAPIC_RTE_MASK_SET;
215+
rte.bits.trigger_mode = IOAPIC_RTE_TRGRMODE_LEVEL;
216+
rte.bits.dest_mode = DEFAULT_DEST_MODE;
217+
rte.bits.delivery_mode = DEFAULT_DELIVERY_MODE;
218+
rte.bits.vector = vr;
216219

217220
/* Fixed to active high */
218-
rte.full |= IOAPIC_RTE_INTAHI;
221+
rte.bits.intr_polarity = IOAPIC_RTE_INTPOL_AHI;
219222

220223
/* Dest field */
221-
rte.full |= (ALL_CPUS_MASK << IOAPIC_RTE_DEST_SHIFT);
224+
rte.bits.dest_field = ALL_CPUS_MASK;
222225
}
223226

224227
return rte;
@@ -233,7 +236,7 @@ static void ioapic_set_routing(uint32_t gsi, uint32_t vr)
233236
rte = create_rte_for_gsi_irq(gsi, vr);
234237
ioapic_set_rte_entry(addr, gsi_table_data[gsi].pin, rte);
235238

236-
if ((rte.full & IOAPIC_RTE_TRGRMOD) != 0UL) {
239+
if (rte.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_LEVEL) {
237240
set_irq_trigger_mode(gsi, true);
238241
} else {
239242
set_irq_trigger_mode(gsi, false);
@@ -322,9 +325,9 @@ ioapic_irq_gsi_mask_unmask(uint32_t irq, bool mask)
322325
if (addr != NULL) {
323326
ioapic_get_rte_entry(addr, pin, &rte);
324327
if (mask) {
325-
rte.full |= IOAPIC_RTE_INTMSET;
328+
rte.bits.intr_mask = IOAPIC_RTE_MASK_SET;
326329
} else {
327-
rte.full &= ~IOAPIC_RTE_INTMASK;
330+
rte.bits.intr_mask = IOAPIC_RTE_MASK_CLR;
328331
}
329332
ioapic_set_rte_entry(addr, pin, rte);
330333
dev_dbg(ACRN_DBG_PTIRQ, "update: irq:%d pin:%hhu rte:%lx",

‎hypervisor/debug/shell.c

Lines changed: 12 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -927,8 +927,8 @@ static void get_entry_info(const struct ptirq_remapping_info *entry, char *type,
927927
(void)strncpy_s(type, 16U, "PIC", 16U);
928928
}
929929
ioapic_get_rte(phys_irq, &rte);
930-
*dest = rte.full >> IOAPIC_RTE_DEST_SHIFT;
931-
if ((rte.full & IOAPIC_RTE_TRGRLVL) != 0UL) {
930+
*dest = rte.bits.dest_field;
931+
if (rte.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_LEVEL) {
932932
*lvl_tm = true;
933933
} else {
934934
*lvl_tm = false;
@@ -1047,13 +1047,13 @@ static void get_vioapic_info(char *str_arg, size_t str_max, uint16_t vmid)
10471047
rte.full = 0UL;
10481048
for (pin = 0U; pin < pincount; pin++) {
10491049
vioapic_get_rte(vm, pin, &rte);
1050-
mask = ((rte.full & IOAPIC_RTE_INTMASK) == IOAPIC_RTE_INTMSET);
1051-
remote_irr = ((rte.full & IOAPIC_RTE_REM_IRR) == IOAPIC_RTE_REM_IRR);
1052-
phys = ((rte.full & IOAPIC_RTE_DESTMOD) == IOAPIC_RTE_DESTPHY);
1053-
delmode = (uint32_t)(rte.full & IOAPIC_RTE_DELMOD);
1054-
level = ((rte.full & IOAPIC_RTE_TRGRLVL) != 0UL);
1055-
vector = rte.u.lo_32 & IOAPIC_RTE_LOW_INTVEC;
1056-
dest = (uint32_t)(rte.full >> IOAPIC_RTE_DEST_SHIFT);
1050+
mask = (rte.bits.intr_mask == IOAPIC_RTE_MASK_SET);
1051+
remote_irr = (rte.bits.remote_irr == IOAPIC_RTE_REM_IRR);
1052+
phys = (rte.bits.dest_mode == IOAPIC_RTE_DESTMODE_PHY);
1053+
delmode = rte.bits.delivery_mode;
1054+
level = (rte.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_LEVEL);
1055+
vector = rte.bits.vector;
1056+
dest = rte.bits.dest_field;
10571057

10581058
len = snprintf(str, size, "\r\n%hhu\t0x%X\t%s\t0x%X\t%s\t%u\t%d\t%d",
10591059
pin, vector, phys ? "phys" : "logic", dest, level ? "level" : "edge",
@@ -1092,18 +1092,6 @@ static int32_t shell_show_vioapic_info(int32_t argc, char **argv)
10921092
return -EINVAL;
10931093
}
10941094

1095-
static void get_rte_info(union ioapic_rte rte, bool *mask, bool *irr,
1096-
bool *phys, uint32_t *delmode, bool *level, uint32_t *vector, uint32_t *dest)
1097-
{
1098-
*mask = ((rte.full & IOAPIC_RTE_INTMASK) == IOAPIC_RTE_INTMSET);
1099-
*irr = ((rte.full & IOAPIC_RTE_REM_IRR) == IOAPIC_RTE_REM_IRR);
1100-
*phys = ((rte.full & IOAPIC_RTE_DESTMOD) == IOAPIC_RTE_DESTPHY);
1101-
*delmode = (uint32_t)(rte.full & IOAPIC_RTE_DELMOD);
1102-
*level = ((rte.full & IOAPIC_RTE_TRGRLVL) != 0UL);
1103-
*vector = (uint32_t)(rte.full & IOAPIC_RTE_INTVEC);
1104-
*dest = (uint32_t)(rte.full >> APIC_ID_SHIFT);
1105-
}
1106-
11071095
/**
11081096
* @brief Get information of ioapic
11091097
*
@@ -1133,18 +1121,13 @@ static int32_t get_ioapic_info(char *str_arg, size_t str_max_len)
11331121
uint32_t pin = ioapic_irq_to_pin(irq);
11341122
union ioapic_rte rte;
11351123

1136-
bool irr, phys, level, mask;
1137-
uint32_t delmode, vector, dest;
1138-
11391124
/* Add NULL check for addr, INVALID_PIN check for pin */
11401125
if ((addr == NULL) || (!ioapic_is_pin_valid(pin))) {
11411126
goto overflow;
11421127
}
11431128

11441129
ioapic_get_rte_entry(addr, pin, &rte);
11451130

1146-
get_rte_info(rte, &mask, &irr, &phys, &delmode, &level, &vector, &dest);
1147-
11481131
len = snprintf(str, size, "\r\n%03d\t%03hhu\t0x%08X\t0x%08X\t", irq, pin, rte.u.hi_32, rte.u.lo_32);
11491132
if (len >= size) {
11501133
goto overflow;
@@ -1153,7 +1136,9 @@ static int32_t get_ioapic_info(char *str_arg, size_t str_max_len)
11531136
str += len;
11541137

11551138
len = snprintf(str, size, "0x%02X\t0x%02X\t%s\t%s\t%u\t%d\t%d",
1156-
vector, dest, phys ? "phys" : "logic", level ? "level" : "edge", delmode >> 8, irr, mask);
1139+
rte.bits.vector, rte.bits.dest_field, rte.bits.dest_mode ? "logic" : "phys",
1140+
rte.bits.trigger_mode ? "level" : "edge", rte.bits.delivery_mode, rte.bits.remote_irr,
1141+
rte.bits.intr_mask);
11571142
if (len >= size) {
11581143
goto overflow;
11591144
}

‎hypervisor/debug/vuart.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -143,7 +143,7 @@ static void vuart_toggle_intr(const struct acrn_vuart *vu)
143143
* modify the vioapic setting, as it's only for debug uart,
144144
* we want to make it as an known issue.
145145
*/
146-
if ((rte.full & IOAPIC_RTE_INTPOL) != 0UL) {
146+
if (rte.bits.intr_polarity == IOAPIC_RTE_INTPOL_ALO) {
147147
operation = (intr_reason != IIR_NOPEND) ? GSI_SET_LOW : GSI_SET_HIGH;
148148
} else {
149149
operation = (intr_reason != IIR_NOPEND) ? GSI_SET_HIGH : GSI_SET_LOW;

0 commit comments

Comments
 (0)