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import board_cfg_lib
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- TOTAL_MEM_SIZE = 4 * 1024 * 1024 * 1024
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+ FOUR_GBYTE = 4 * 1024 * 1024 * 1024
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LOW_MEM_TO_PCI_HOLE = 0x20000000
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@@ -22,18 +22,27 @@ def ve820_per_launch(config, hpa_size):
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board_name = board_cfg_lib .undline_name (board_name )
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+ high_mem_hpa_len = 0x0
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low_mem_to_pci_hole_len = '0xA0000000'
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low_mem_to_pci_hole = '0x20000000'
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pci_hole_addr = '0xe0000000'
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pci_hole_len = '0x20000000'
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start_low_hpa = 0x100000
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- hpa_len = int (hpa_size , 16 ) - 1 * 1024 * 1024
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+ if (int (hpa_size , 16 ) <= 512 * 1024 * 1024 ):
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+ low_mem_hpa_len = int (hpa_size , 16 ) - 1 * 1024 * 1024
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+ else :
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+ low_mem_hpa_len = 511 * 1024 * 1024
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+ high_mem_hpa_len = int (hpa_size , 16 ) - 512 * 1024 * 1024
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# pre_launch memroy: mem_size is the ve820 length
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print ("#include <e820.h>" , file = config )
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print ("#include <vm.h>" , file = config )
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print ("" , file = config )
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- print ("#define VE820_ENTRIES_{}\t {}U" .format (board_name , 5 ), file = config )
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+ if (high_mem_hpa_len == 0 ):
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+ print ("#define VE820_ENTRIES_{}\t {}U" .format (board_name , 5 ), file = config )
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+ else :
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+ print ("#define VE820_ENTRIES_{}\t {}U" .format (board_name , 6 ), file = config )
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+
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print ("static const struct e820_entry ve820_entry[{}] = {{" .format (
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"VE820_ENTRIES_{}" .format (board_name )), file = config )
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print ("\t {\t /* usable RAM under 1MB */" , file = config )
@@ -54,7 +63,7 @@ def ve820_per_launch(config, hpa_size):
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print ("\t \t .baseaddr = {}UL,\t \t /* 1MB */" .format (
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hex (start_low_hpa )), file = config )
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print ("\t \t .length = {}UL,\t /* {}MB */" .format (
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- hex (hpa_len ), hpa_len / 1024 / 1024 ), file = config )
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+ hex (low_mem_hpa_len ), low_mem_hpa_len / 1024 / 1024 ), file = config )
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print ("\t \t .type = E820_TYPE_RAM" , file = config )
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print ("\t }," , file = config )
@@ -68,14 +77,24 @@ def ve820_per_launch(config, hpa_size):
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print ("\t \t .type = E820_TYPE_RESERVED" , file = config )
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print ("\t }," , file = config )
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print ("" , file = config )
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- print ("\t {{\t /* between PCI hole and {}GB */" .format (
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- TOTAL_MEM_SIZE / 1024 / 1024 / 1024 ), file = config )
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+ print ("\t {\t /* between PCI hole and 4 GB */" , file = config )
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print ("\t \t .baseaddr = {}UL,\t /* {}GB */" .format (
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hex (int (pci_hole_addr , 16 )), int (pci_hole_addr , 16 ) / 1024 / 1024 / 1024 ), file = config )
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print ("\t \t .length = {}UL,\t /* {}MB */" .format (
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hex (int (pci_hole_len , 16 )), int (pci_hole_len , 16 ) / 1024 / 1024 ), file = config )
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print ("\t \t .type = E820_TYPE_RESERVED" , file = config )
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print ("\t }," , file = config )
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+ print ("" , file = config )
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+ if (high_mem_hpa_len != 0 ):
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+ print ("\t {\t /* high mem after 4GB*/" , file = config )
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+ print ("\t \t .baseaddr = {}UL,\t /* 4 GB */" .format (
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+ hex (FOUR_GBYTE )), file = config )
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+ print ("\t \t .length = {}UL,\t /* {}MB */" .format (
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+ hex (high_mem_hpa_len ), high_mem_hpa_len / 1024 / 1024 ), file = config )
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+ print ("\t \t .type = E820_TYPE_RAM" , file = config )
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+ print ("\t }," , file = config )
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+ print ("" , file = config )
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+
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print ("};" , file = config )
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print ("" , file = config )
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print ("/**" , file = config )
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